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{{Short description|Series of x86 manycore processors from Intel}}{{distinguish|text= the ATI Xenos, Xenon or Xeon}}{{Use dmy dates|date=October 2020}}

factoids

| slowest = 1.053| fastest = 1.7| numcores = 32-72Kilobyte>KB per coreKilobyte>KB per core| created =45 nanometer>45 nm transistors14 nanometer>14 nm transistors (tri-gate)IA-32, x86-64HTTPS://ENGINEERING.PURDUE.EDU/~EIGENMAN/ECE563/HANDOUTS/INTEL-XEON-PHI-SYSTEMSOFTWAREDEVELOPERSGUIDE.PDF#PAGE=16ARCHIVE-DATE=21 APR 2024TITLE=INTEL® XEON PHIâ„¢ COPROCESSOR SYSTEM SOFTWARE DEVELOPERS GUIDE DATE=8 NOV 2012PAGES=16, Advanced Vector Extensions>AVX, AVX2, AVX-512| sock1 = LGA 3647| sock2 = PCI Express 3.0 x16Xeon Phi 3100Xeon Phi 7100|Xeon Phi 7200}}| predecessor = | successor = designfirm=Intelmemory1=Up to DDR4 115.4 GB/s with ECC supportcaption=Xeon Phi 5100 without heatsinkcore1=Knights Ferrycore3=Knights Landingcore5=Knights Hillmicroarch=Larrabee}}Xeon Phi is a discontinued series of x86 manycore processors designed and made by Intel. It was intended for use in supercomputers, servers, and high-end workstations. Its architecture allowed use of standard programming languages and application programming interfaces (APIs) such as OpenMP.WEB,weblink Best Known Methods for Using OpenMP on Intel Many Integrated Core (Intel MIC) Architecture, robert-reed, 4 February 2013, software.intel.com, BOOK, Jeffers, James, Reinders, James, Intel Xeon Phi Coprocessor High Performance Programming, Morgan Kaufmann, 1 March 2013, 978-0124104143, Xeon Phi launched in 2010. Since it was originally based on an earlier GPU design (codenamed "Larrabee") by IntelWEB,weblink Intel Quietly Kills Off Xeon Phi, Joel, Hruska, 8 May 2019, ExtremeTech, that was cancelled in 2009,WEB,weblink Intel scraps graphics chip based on Larrabee, 6 December 2009, Reuters, it shared application areas with GPUs. The main difference between Xeon Phi and a GPGPU like Nvidia Tesla was that Xeon Phi, with an x86-compatible core, could, with less modification, run software that was originally targeted to a standard x86 CPU.Initially in the form of PCI Express-based add-on cards, a second-generation product, codenamed Knights Landing, was announced in June 2013.JOURNAL, Sodani, Avinash, etal, Knights Landing: Second-Generation Intel Xeon Phi Product, IEEE Micro, 36, 2, 2016, 34–46, 10.1109/MM.2016.25, 28837176, These second-generation chips could be used as a standalone CPU, rather than just as an add-in card.File:Tianhe-2.jpg|thumb|The Tianhe-2Tianhe-2In June 2013, the Tianhe-2 supercomputer at the National Supercomputer Center in Guangzhou (NSCC-GZ) was announcedWEB, TOP500 - June 2013,weblink TOP500, 18 June 2013, as the world's fastest supercomputer ({{As of|2023|06|lc=y}}, it is {{Numero|10}}WEB, June 2023 {{!, TOP500 Supercomputer Sites |url=https://www.top500.org/lists/top500/list/2023/06/ |access-date= |website=www.top500.org |language=en}}). It used Intel Xeon Phi coprocessors and Ivy Bridge-EP Xeon E5 v2 processors to achieve 33.86 petaFLOPS.WEB,weblink Intel Powers the World's Fastest Supercomputer, Reveals New and Future High Performance Computing Technologies, 21 June 2013, The Xeon Phi product line directly competed with Nvidia's Tesla and AMD Radeon Instinct lines of deep learning and GPGPU cards. It was discontinued due to a lack of demand and Intel's problems with its 10nm node.WEB,weblink Intel is Giving up on Xeon Phi - Eight More Models Declared End-Of-Life, W1zzard, 24 July 2018, TechPowerUp,

History{| class"wikitable"

! Code name !! Process !! Comments| offered as PCI Express card; derived from Larrabee project| derived from P54C; vector processing unit; first device to be announced as Xeon Phi; AVX-512-like encodingAUTHOR=MARC SAUTERLANGUAGE=DE, www.golem.de, AVX-512| nearly identical to Knights Landing but optimized for deep learning| cancelled(File:Intel Xeon Phi Lineup.jpg|thumb|A lineup of the Xeon Phi coprocessors. From the left; Knights Ferry, Knights Corner, Knights Landing.)

Background

The Larrabee microarchitecture (in development since 2006{{citation |url=https://www.theinquirer.net/inquirer/news/1029138/new-from-intel-its-mini-cores |archive-url=https://web.archive.org/web/20090829084338weblink |url-status=unfit |archive-date=29 August 2009 |title= New from Intel: It's Mini-Cores! |author= Charlie Demerjian |date= 3 July 2006 |work= theinquirer.net |publisher= The Inquirer}}) introduced very wide (512-bit) SIMD units to a x86 architecture based processor design, extended to a cache-coherent multiprocessor system connected via a ring bus to memory; each core was capable of four-way multithreading. Due to the design being intended for GPU as well as general purpose computing, the Larrabee chips also included specialised hardware for texture sampling.JOURNAL, Cavin, D., Espasa, E., Grochowski, T., Juan, M., Hanrahan, P., Carmean, S., Sprangle, A., Forsyth, J., August 2008, Larrabee: A Many-Core x86 Architecture for Visual Computing,weblink ACM Transactions on Graphics, Proceedings of ACM SIGGRAPH 2008, 27, 3, 18:11, 10.1145/1360612.1360617, 0730-0301, L., Seiler, R., Abrash, R., Dubey, E., Junkins, T., Lake, P., Sugerman, 52799248, 2008-08-06,weblink 2015-09-10, dead, {{citation|url=https://www.stanford.edu/class/ee380/Abstracts/100106-slides.pdf|title= SIMD Programming with Larrabee|author= Tom Forsyth|publisher= Intel}} The project to produce a retail GPU product directly from the Larrabee research project was terminated in May 2010.{{citation|url=weblink|title= Intel Kills Larrabee GPU, Will Not Bring a Discrete Graphics Product to Market|author= Ryan Smith|date= 25 May 2010AnandTech >website= www.anandtech.com}}Another contemporary Intel research project implementing x86 architecture on a many-multicore processor was the 'Single-chip Cloud Computer' (prototype introduced 2009{{citation|url=https://www.pcworld.com/article/183653/intel_48core_singlechip_cloud_computer_improves_power_efficiency.html |title= Intel 48-Core "Single-Chip Cloud Computer" Improves Power Efficiency |author= Tony Bradley |publisher= PCWorld |work= pcworld.com |date= 3 December 2009}}), a design mimicking a cloud computing computer datacentre on a single chip with multiple independent cores: the prototype design included 48 cores per chip with hardware support for selective frequency and voltage control of cores to maximize energy efficiency, and incorporated a mesh network for inter-chip messaging. The design lacked cache-coherent cores and focused on principles that would allow the design to scale to many more cores.{{citation|url=weblink |title= Intel Research : Single-Chip Cloud Computer |publisher= Intel |work= techresearch.intel.com}}The Teraflops Research Chip (prototype unveiled 2007{{citation |url=weblink |title= Intel Tests Chip Design With 80-Core Processor |author= Ben Ames |publisher= IDG News |date= 11 February 2007 |work= pcworld.com |access-date= 14 November 2018 |archive-date= 17 January 2012 |archive-url=weblink |url-status= dead }}) is an experimental 80-core chip with two floating-point units per core, implementing a 96-bit VLIW architecture instead of the x86 architecture.WEB,weblink Intel Details 80-Core Teraflops Research Chip - X-bit labs, xbitlabs.com, 27 August 2015, dead,weblink" title="web.archive.org/web/20150205070552weblink">weblink 5 February 2015, The project investigated intercore communication methods, per-chip power management, and achieved 1.01 TFLOPS at 3.16 GHz consuming 62 W of power.{{citation|url=https://download.intel.com/pressroom/kits/Teraflops/Teraflops_Research_Chip_Overview.pdf |title= Intel's Teraflops Research Chip |publisher= Intel |work= download.intel.com |archive-url=https://web.archive.org/web/20210516003332weblink |archive-date=2021-05-16 |url-status=dead}}{{citation |url=weblink |title= Intel Details 80-Core Teraflops Research Chip |author= Anton Shilov |date= 12 February 2007 |publisher= Xbit laboratories |work= xbitlabs.com |url-status= dead |archive-url=weblink" title="web.archive.org/web/20150205070552weblink">weblink |archive-date= 5 February 2015}}

{{anchor|Knights Ferry}}Knights Ferry

Intel's Many Integrated Core (MIC) prototype board, named Knights Ferry, incorporating a processor codenamed Aubrey Isle was announced 31 May 2010. The product was stated to be a derivative of the Larrabee project and other Intel research including the Single-chip Cloud Computer.{{citation |url=weblink |title= Intel unveils many-core Knights platform for HPC |author= Rupert Goodwins |publisher= ZDNet |date= 1 June 2010 |work= zdnet.co.uk}}{{citation |url=weblink |title= Intel News Release : Intel Unveils New Product Plans for High-Performance Computing |date= 31 May 2010 |work= intel.com |publisher= Intel}}The development product was offered as a PCIe card with 32 in-order cores at up to 1.2 GHz with four threads per core, 2 GB GDDR5 memory,{{citation|title=Runners and riders in GPU steeplechase|date=24 June 2010|url=http://people.maths.ox.ac.uk/gilesm/talks/nag_tpc10.pdf|author=Mike Giles|work=people.maths.ox.ac.uk|pages=8–10}} and 8 MB coherent L2 cache (256 KB per core with 32 KB L1 cache), and a power requirement of ~300 W, built at a 45 nm process. In the Aubrey Isle core a 1,024-bit ring bus (512-bit bi-directional) connects processors to main memory.{{citation |url=weblink |title= Intel Many Integrated Core Architecture |date= December 2010 |publisher= Intel |work= many-core.group.cam.ac.uk |url-status= dead |archive-url=weblink" title="web.archive.org/web/20120402211714weblink">weblink |archive-date= 2 April 2012}} Single-board performance has exceeded 750 GFLOPS. The prototype boards only support single-precision floating-point instructions.{{citation |url=weblink |title= OEMs show systems with Intel MIC chips |author= Rick Merritt |date=20 June 2011 |work=EE Times}}Initial developers included CERN, Korea Institute of Science and Technology Information (KISTI) and Leibniz Supercomputing Centre. Hardware vendors for prototype boards included IBM, SGI, HP, Dell and others.{{citation |url=weblink |title= Intel Shows MIC Progress |date= 18 July 2011 |author= Tom R. Halfhill |work= linleygroup.com|publisher= The Linley Group}}

Knights Corner

The Knights Corner product line is made at a 22 nm process size, using Intel's Tri-gate technology with more than 50 cores per chip, and is Intel's first many-cores commercial product.{{citation |url=weblink |title= Intel pushes for HPC space with Knights Corner |publisher= Net Communities Limited, UK |work= thinq.co.uk |date= 20 June 2011 |author= Gareth Halfacree}}In June 2011, SGI announced a partnership with Intel to use the MIC architecture in its high-performance computing products.{{citation |url=weblink |title= SGI wants Intel for super supercomputer |date= 20 June 2011 |author= Andrea Petrou |work= news.techeye.net |url-status= dead |archive-url=weblink" title="web.archive.org/web/20110916013050weblink">weblink |archive-date= 16 September 2011}} In September 2011, it was announced that the Texas Advanced Computing Center (TACC) will use Knights Corner cards in their 10-petaFLOPS "Stampede" supercomputer, providing 8 petaFLOPS of compute power.PRESS RELEASE,weblink "Stampede's" Comprehensive Capabilities to Bolster U.S. Open Science Computational Resources, 22 September 2011, Texas Advanced Computing Center, 23 September 2011, 5 August 2012,weblink" title="web.archive.org/web/20120805125957weblink">weblink dead, According to "Stampede: A Comprehensive Petascale Computing Environment" the "second-generation Intel (Knights Landing) MICs will be added when they become available, increasing Stampede's aggregate peak performance to at least 15 PetaFLOPS."WEB,weblink Stampede: A Comprehensive Petascale Computing Environment, IEEE Cluster 2011 Special Topic, 16 November 2011, dead,weblink 26 September 2012, On 15 November 2011, Intel showed an early silicon version of a Knights Corner processor.{{citation|url=https://www.tomshardware.com/news/intel-knights-corner-mic-co-processor,14002.html |title=Intel's Knights Corner: 50+ Core 22nm Co-processor|access-date=16 November 2011 |date=16 November 2011 |first= Marcus |last=Yam |work= tomshardware.com |publisher=Tom's Hardware}}{{citation|url=https://www.eetimes.com/electronics-news/4230654/Intel-unveils-1-TFLOP-s-Knight-s-Corner |title=Intel unveils 1 TFLOP/s Knights Corner|access-date=16 November 2011 |author= Sylvie Barak |date= 16 November 2011 |work=EE Times}}On 5 June 2012, Intel released open source software and documentation regarding Knights Corner.{{citation|url=https://software.intel.com/en-us/blogs/2012/06/05/knights-corner-open-source-software-stack|title=Knights Corner: Open source software stack |publisher= Intel|author= James Reinders |date= 5 June 2012}}On 18 June 2012, Intel announced at the 2012 Hamburg International Supercomputing Conference that Xeon Phi will be the brand name used for all products based on their Many Integrated Core architecture.NEWS,weblink Chip Shot: Intel Names the Technology to Revolutionize the Future of HPC - Intel Xeon Phi Product Family, 18 June 2012, Intel, Radek, 12 December 2012, {{citation |url=weblink |title= Intel slaps Xeon Phi brand on MIC coprocessors |first= Timothy |last= Prickett Morgan |date= 18 June 2012 |work= 222.theregister.co.uk}}{{citation |url=weblink |title= Latest Intel Xeon Processors E5 Product Family Achieves Fastest Adoption of New Technology on Top500 List |date= 18 June 2012 |quote= Intel Xeon Phi is the new brand name for all future Intel Many Integrated Core Architecture based products targeted at HPC, enterprise, datacenters and workstations. The first Intel Xeon Phi product family member is scheduled for volume production by the end of 2012 |author= Intel Corporation |work= marketwatch.com |access-date= 18 June 2012 |archive-date= 20 June 2012 |archive-url=weblink" title="web.archive.org/web/20120620222352weblink">weblink |url-status= dead }}NEWS, Intel Xeon Phi coprocessors accelerate the pace of discovery and innovation, Raj Hazra, Intel,weblink 18 June 2012, 12 December 2012, NEWS, Cray will use Intel MIC, branded Xeon Phi, Rick Merritt, EETimes,weblink 18 June 2012, 12 December 2012, NEWS, Intel christens its 'Many Integrated Core' products Xeon Phi, eyes exascale milestone, Terrence O'Brien, Engadget,weblink 18 June 2012, 12 December 2012, NEWS, Intel Wraps Xeon Phi Branding Around MIC Coprocessors, Jeffrey Burt, eWeek,weblink 18 June 2012, 7 March 2022, In June 2012, Cray announced it would be offering 22 nm 'Knight's Corner' chips (branded as 'Xeon Phi') as a co-processor in its 'Cascade' systems.{{citation |url=weblink |work= eetimes.com |title= Cray will use Intel MIC, branded Xeon Phi |first= Rick |last= Merritt |date= 8 June 2012}}{{citation |url=weblink |archive-url=weblink" title="web.archive.org/web/20120622064502weblink">weblink |url-status= unfit |archive-date= 22 June 2012 |title= Cray to support Intel's Xeon Phi in Cascade clusters |first= Lawrence|last= Latif |date= 19 June 2012 |work= theinquirer.net}}In June 2012, ScaleMP announced a virtualization update allowing Xeon Phi as a transparent processor extension, allowing legacy MMX/SSE code to run without code changes.PRESS RELEASE,weblink ScaleMP vSMP Foundation to Support Intel Xeon Phi, ScaleMP, 20 June 2012,weblink" title="web.archive.org/web/20130520072517weblink">weblink 2013-05-20, dead, An important component of the Intel Xeon Phi coprocessor's core is its vector processing unit (VPU).WEB,weblink Intel Xeon Phi X100 Family Coprocessor - the Architecture, George Chrysos, 12 November 2012, software.intel.com, The VPU features a novel 512-bit SIMD instruction set, officially known as Intel Initial Many Core Instructions (Intel IMCI). Thus, the VPU can execute 16 single-precision (SP) or 8 double-precision (DP) operations per cycle. The VPU also supports Fused Multiply-Add (FMA) instructions and hence can execute 32 SP or 16 DP floating point operations per cycle. It also provides support for integers.The VPU also features an Extended Math Unit (EMU) that can execute operations such as reciprocal, square root, and logarithm, thereby allowing these operations to be executed in a vector fashion with high bandwidth. The EMU operates by calculating polynomial approximations of these functions.On 12 November 2012, Intel announced two Xeon Phi coprocessor families using the 22 nm process size: the Xeon Phi 3100 and the Xeon Phi 5110P.NEWS,weblink Intel Delivers New Architecture for Discovery with Intel Xeon Phi Coprocessors, 12 November 2012, Intel, IntelPR, 12 December 2012, MAGAZINE, Intel ships 60-core Xeon Phi processor, Agam Shah, Computerworld,weblink 12 November 2012, 12 December 2012, 12 March 2013,weblink" title="web.archive.org/web/20130312145710weblink">weblink dead, NEWS, The Xeon Phi at work at TACC, Johan De Gelas, AnandTech,weblink 14 November 2012, 12 December 2012, The Xeon Phi 3100 will be capable of more than 1 teraFLOPS of double-precision floating-point instructions with 240 GB/s memory bandwidth at 300 W. The Xeon Phi 5110P will be capable of 1.01 teraFLOPS of double-precision floating-point instructions with 320 GB/s memory bandwidth at 225 W. The Xeon Phi 7120P will be capable of 1.2 teraFLOPS of double-precision floating-point instructions with 352 GB/s memory bandwidth at 300 W.On 17 June 2013, the Tianhe-2 supercomputer was announced by TOP500 as the world's fastest. Tianhe-2 used Intel Ivy Bridge Xeon and Xeon Phi processors to achieve 33.86 petaFLOPS. It was the fastest on the list for two and a half years, lastly in November 2015.WEB, Tianhe-2 (MilkyWay-2), Top500.org,weblinkaccess-date=6 May 2016,

Design and programming

The cores of Knights Corner are based on a modified version of P54C design, used in the original Pentium.WEB,weblink Intel's 50-core champion: In-depth on Xeon Phi, Hruska, Joel, 30 July 2012, ExtremeTech, Ziff Davis, Inc., 2 December 2012, The basis of the Intel MIC architecture is to leverage x86 legacy by creating an x86-compatible multiprocessor architecture that can use existing parallelization software tools. Programming tools include OpenMP,CONFERENCE, Barker, J, Bowden, J, 2013, Manycore Parallelism through OpenMP, IWOMP, OpenMP in the Era of Low Power Devices and Accelerators, Springer, Lecture Notes in Computer Science, vol 8122, 8122, 45–57, 10.1007/978-3-642-40698-0_4, 978-3-642-40697-3, OpenCL,{{citation |url=weblink |title= OEMs show systems with Intel MIC chips |author= Rick Merritt |date= 20 June 2011 |work= EE Times}} Cilk/Cilk Plus and specialised versions of Intel's Fortran, C++{{citation |arxiv= 1211.5530|title= Efficient Hybrid Execution of C++ Applications using Intel Xeon Phi Coprocessor |date= 23 November 2012|bibcode= 2012arXiv1211.5530D|last1= Dokulil |first1= Jiri |last2= Bajrovic |first2= Enes |last3= Benkner |first3= Siegfried |last4= Pllana |first4= Sabri |last5= Sandrieser |first5= Martin |last6= Bachmayer |first6= Beverly }} and math libraries.{{citation|url=https://newsroom.intel.com/servlet/JiveServlet/download/2152-4-5220/ISC_Intel_MIC_factsheet.pdf |title=News Fact Sheet: Intel Many Integrated Core (Intel MIC) Architecture ISC'11 Demos and Performance Description |work=newsroom.intel.com |publisher=Intel |date=20 June 2011 |url-status=dead |archive-url=https://web.archive.org/web/20120324101552weblink |archive-date=24 March 2012 }}Design elements inherited from the Larrabee project include x86 ISA, 4-way SMT per core, 512-bit SIMD units, 32 KB L1 instruction cache, 32 KB L1 data cache, coherent L2 cache (512 KB per coreTesla vs. Xeon Phi vs. Radeon. A Compiler Writer’s Perspective // The Portland Group (PGI), CUG 2013 Proceedings), and ultra-wide ring bus connecting processors and memory.The Knights Corner 512-bit SIMD instructions share many intrinsic functions with AVX-512 extension . The instruction set documentation is available from Intel under the extension name of KNC.WEB,weblink Intel Many Integrated Core Architecture (Intel MIC Architecture) - RESOURCES (including downloads), Intel, 6 January 2014, WEB,weblink Intel Xeon Phi Coprocessor Instruction Set Architecture Reference Manual, Intel, 7 September 2012, 6 January 2014, WEB,weblink Intel Developer Zone: Intel Xeon Phi Coprocessor, Intel, 6 January 2014,weblink 1 February 2014, dead, WEB, Intel® Intrinsics Guide,weblink 2020-08-04, software.intel.com, {| class="wikitable sortable"|+Models of Xeon Phi X100 Series!rowspan="2" | Name!rowspan="2" | Serial Code!rowspan="2" | Cores(Threads @ 4× core)!colspan="2" | Clock (MHz)!rowspan="2" | L2cache! colspan="3" | GDDR5 ECC memory!rowspan="2" | Peak DPcompute(GFLOPS)!rowspan="2" | TDP(W)!rowspan="2" | Coolingsystem!rowspan="2" | Form factor!rowspan="2" | Released! class="unsortable" | Base! class="unsortable" | Turbo! Quantity! Channels!colspan="1" | BWGB/s Xeon Phi 3110XHTTPS://WWW.SABREPC.COM/INTEL-SE3110X-XEON-PHI-3110X-KNIGHTS-CORNER-COPROCESSOR.HTML>TITLE=INTEL SE3110X XEON PHI 3110X KNIGHTS CORNER 6GB COPROCESSOR-NO COOLING -SABREPC.COM -SABREPC.COMLANGUAGE=ENARCHIVE-URL=HTTPS://WEB.ARCHIVE.ORG/WEB/20170222200102/HTTPS://WWW.SABREPC.COM/INTEL-SE3110X-XEON-PHI-3110X-KNIGHTS-CORNER-COPROCESSOR.HTMLURL-STATUS=DEAD, SE3110X {{0}}61 (244) 1053 - 30.5 MB|{{0}}6 GB |12|240 1028 300 Bare board PCIe 2.0 x16 card November, 2012|{{0}}8 GB|16|320 ACCESS-DATE=2017-02-22, Intel ARK (Product Specs), |SC3120A| {{0}}57 (228)| 1100| -| 28.5 MB| {{0}}6 GB| 12| 240| 1003| 300| Fan/heatsink| 17 June 2013ACCESS-DATE=2017-02-22, Intel ARK (Product Specs), | SC3120P| {{0}}57 (228)| 1100| -| 28.5 MB| {{0}}6 GB| 12| 240 | 1003| 300| Passive heatsink| 17 June 2013WEBSITE=WWW.CPU-WORLD.COM, 2024-04-21, |BC31S1P|{{0}}57 (228)| 1100| -|28.5 MB|{{0}}8 GB|16|320 |1003|270|Passive heatsink|17 June 2013ACCESS-DATE=2017-02-22, Intel ARK (Product Specs), |SC5110P|{{0}}60 (240)| 1053| -|30.0 MB|{{0}}8 GB|16|320 |1011|225|Passive heatsink|12 Nov 2012 Xeon Phi 5120DHTTPS://ARK.INTEL.COM/PRODUCTS/75801/INTEL-XEON-PHI-COPROCESSOR-5120D-8GB-1_053-GHZ-60-CORE>TITLE=INTEL XEON PHI COPROCESSOR 5120D (8GB, 1.053 GHZ, 60 CORE) PRODUCT SPECIFICATIONSNEWSPAPER=INTEL ARK (PRODUCT SPECS), | SC5120D {{0}}60 (240) 1053 - 30.0 MB {{0}}8 GB 16 352 1011 245 Bare board SFF 230-pin card 17 June 2013| BC5120DWEBSITE=WWW.CPU-WORLD.COM, 2024-04-21, |SE10P|{{0}}61 (244)| 1100| -|30.5 MB|{{0}}8 GB|16|352 |1074|300|Passive heatsink PCIe 2.0 x16 card|12 Nov. 2012WEBSITE=WWW.CPU-WORLD.COM, 2024-04-21, |SE10X|{{0}}61 (244)| 1100| -|30.5 MB|{{0}}8 GB|16|352 |1074 |300|Bare board|12 Nov. 2012WEBSITE=WWW.SABREPC.COMACCESS-DATE=2017-02-22, |SC7110P|{{0}}61 (244)| 1100| 1250|30.5 MB|16 GB|16|352 |1220 |300|Passive heatsink|??? WEBSITE=WWW.SABREPC.COMACCESS-DATE=2017-02-22, |SC7110X|{{0}}61 (244)| 1250| ???|30.5 MB|16 GB|16|352 |1220|300|Bare board|???ACCESS-DATE=2017-02-22, Intel ARK (Product Specs), |SC7120A|{{0}}61 (244)| 1238| 1333| 30.5 MB| 16 GB | 16| 352 | 1208 | 300| Fan/heatsink| 6 April 2014ACCESS-DATE=2017-02-22, Intel ARK (Product Specs), |SC7120D|{{0}}61 (244)| 1238| 1333| 30.5 MB| 16 GB | 16| 352| 1208 | 270| Bare board| SFF 230-pin card| March ??, 2014ACCESS-DATE=2017-02-22, Intel ARK (Product Specs), |SC7120P|{{0}}61 (244)|1238|1333|30.5 MB|16 GB|16|352 |1208|300|Passive heatsink PCIe 2.0 x16 card|17 June 2013ACCESS-DATE=2017-02-22, Intel ARK (Product Specs), |SC7120X|{{0}}61 (244)|1238|1333|30.5 MB|16 GB |16|352 |1208 |300|Bare board|17 June 2013

Knights Landing

(File:Intel@14nm@Xeon Phi@Knights Landing@Xeon(ES)@QHL6 DSCx1.jpg|thumb|Intel Xeon Phi Knights Landing engineering sample)(File:Intel@14nm@Xeon Phi@Knights Landing@Xeon(ES)@QHL6 DSCx3.jpg|thumb|The same processor, delidded)(File:Intel@14nm@Xeon Phi@Knights Landing@Xeon(ES)@QHL6 DSCx7@5x.jpg|thumb|Die shot)Code name for the second-generation MIC architecture product from Intel. Intel officially first revealed details of its second-generation Intel Xeon Phi products on 17 June 2013. Intel said that the next generation of Intel MIC Architecture-based products will be available in two forms, as a coprocessor or a host processor (CPU), and be manufactured using Intel's 14 nm process technology. Knights Landing products will include integrated on-package memory for significantly higher memory bandwidth.Knights Landing contains up to 72 Airmont (Atom) cores with four threads per core,WEB,weblink Intel Xeon Phi 'Knights Landing' Features Integrated Memory With 500 GB/s Bandwidth and DDR4 Memory Support - Architecture Detailed, WCCFtech, 27 August 2015, 2013-11-25, {{citation |url=https://www.extremetech.com/extreme/171678-intel-unveils-72-core-x86-knights-landing-cpu-for-exascale-supercomputing |title=Intel unveils 72-core x86 Knights Landing CPU for exascale supercomputing |date=26 November 2013 |author=Sebastian Anthony |publisher= ExtremeTech}} using LGA 3647 socketTom's Hardware: Intel Xeon Phi Knights Landing Now Shipping; Omni Path Update, Too. 20 June 2016 supporting up to 384 GB of "far" DDR4 2133 RAM and 8–16 GB of stacked "near" 3D MCDRAM, a version of the Hybrid Memory Cube. Each core has two 512-bit vector units and supports AVX-512 SIMD instructions, specifically the Intel AVX-512 Foundational Instructions (AVX-512F) with Intel AVX-512 Conflict Detection Instructions (AVX-512CD), Intel AVX-512 Exponential and Reciprocal Instructions (AVX-512ER), and Intel AVX-512 Prefetch Instructions (AVX-512PF). Support for IMCI has been removed in favor of AVX-512.{{citation |url=https://software.intel.com/en-us/blogs/2013/avx-512-instructions |title=AVX-512 Instructions |date=23 July 2013 |author=James Reinders |publisher= Intel}}The National Energy Research Scientific Computing Center announced that Phase 2 of its newest supercomputing system "Cori" would use Knights Landing Xeon Phi coprocessors.WEB,weblink Cori, www.nersc.gov, 14 November 2018, 17 May 2019,weblink dead, On 20 June 2016, Intel launched the Intel Xeon Phi product family x200 based on the Knights Landing architecture, stressing its applicability to not just traditional simulation workloads, but also to machine learning.WEB,weblink 2016 ISC High Performance: Intel's Rajeeb Hazra Delivers Keynote Address, Vimeo, WEB,weblink How Intel Xeon Phi Processors Benefit Machine Learning/Deep Learning Apps and Frameworks, Pradeep Dubey, 20 June 2016, software.intel.com, The model lineup announced at launch included only Xeon Phi of bootable form-factor, but two versions of it: standard processors and processors with integrated Intel Omni-Path architecture fabric.WEB,weblink Introducing the Intel Xeon Phi Processor – Your Path to Deeper Insight, Intel,weblink 27 January 2017, dead, The latter is denoted by the suffix F in the model number. Integrated fabric is expected to provide better latency at a lower cost than discrete high-performance network cards.On 14 November 2016, the 48th list of TOP500 contained two systems using Knights Landing in the Top 10.WEB,weblink TOP500_List November 2016, The PCIe based co-processor variant of Knight's Landing was never offered to the general market and was discontinued by August 2017.NEWS, Larabel, Michael, Intel Quietly Drops Xeon Phi 7200 Coprocessors,weblink 25 August 2017, Phoronix, 24 August 2017, This included the 7220A, 7240P and 7220P coprocessor cards.Intel announced they were discontinuing Knights Landing in summer 2018.WEB,weblink Product Change Notification 116378 - 00, 25 July 2018, Intel.com,

Models

All models can boost to their peak speeds, adding 200 MHz to their base frequency when running just one or two cores. When running from three to the maximum number of cores, the chips can only boost 100 MHz above the base frequency. All chips run high-AVX code at a frequency reduced by 200 MHz.WEB, Intel Xeon Phi processor: Your Path to Deeper Insight,weblink Intel.com, 25 February 2017,weblink 26 February 2017, dead, {| class="wikitable sortable"|+Models of Xeon Phi X200 Coprocessor Series! rowspan="2" | Name! rowspan="2" | Serial Code! rowspan="2" | Cores(Threads @ 4× core)! colspan="2" | Clock (MHz)! rowspan="2" | L2cache! colspan="2" | MCDRAM memory! colspan="2" |DDR4 memory! rowspan="2" | TDP(W)! rowspan="2" | Coolingsystem! rowspan="2" | Form factor! rowspan="2" | Released! class="unsortable" | Base! class="unsortable" | Turbo! Quantity! BW! colspan="1" | Capacity!BWweblink |SC7220A68 (272) 1200 140034 MB16 GB400+ GB/s384 GB 102.4 GB/s275|Active heatsink PCIe 3.0 x16 card???weblink |SC7220PPassive heatsinkweblink |SC7240P| 1300| 1500{| class="wikitable sortable"|+Models of Xeon Phi X200 CPU Series! rowspan="2" | Xeon Phi7200 Series! rowspan="2" | sSpecnumber! rowspan="2" | Cores(Threads)! colspan="2" | Clock (MHz)! rowspan="2" | L2cache! colspan="2" | MCDRAM memory! colspan="2" | DDR4 memory! rowspan="2" | Peak DPcompute! rowspan="2" | TDP(W)! rowspan="2" class="unsortable" | Socket! rowspan="2" class="unsortable" | Release date! rowspan="2" | Part number! class="unsortable" | Base! class="unsortable" | Turbo! class="unsortable" | Quantity! class="unsortable" | BW! class="unsortable" | Capacity! class="unsortable" | BW Xeon Phi 7210HTTPS://ARK.INTEL.COM/PRODUCTS/94033/INTEL-XEON-PHI-PROCESSOR-7210-16GB-1_30-GHZ-64-CORE>TITLE=INTEL XEON PHI PROCESSOR 7210 (16GB, 1.30 GHZ, 64 CORE) PRODUCT SPECIFICATIONSWORK=INTEL ARK (PRODUCT SPECS), | SR2ME (B0) 64 (256) 1300 1500 32 MB 16 GB 400+ GB/s384 GB 102.4 GB/s 2662GFLOPS 215 SVLCLGA3647 20 June 2016 HJ8066702859300| SR2X4 (B0)ACCESS-DATE=2017-02-22, Intel ARK (Product Specs), | SR2X5 (B0)| 230| HJ8066702975000 Xeon Phi 7230HTTPS://ARK.INTEL.COM/PRODUCTS/94034/INTEL-XEON-PHI-PROCESSOR-7230-16GB-1_30-GHZ-64-CORE>TITLE=INTEL XEON PHI PROCESSOR 7230 (16GB, 1.30 GHZ, 64 CORE) PRODUCT SPECIFICATIONSWORK=INTEL ARK (PRODUCT SPECS), | SR2MF (B0) 215 HJ8066702859400| SR2X3 (B0)ACCESS-DATE=2017-02-22, Intel ARK (Product Specs), | SR2X2 (B0)| 230| HJ8066702269002 Xeon Phi 7250HTTPS://ARK.INTEL.COM/PRODUCTS/94035/INTEL-XEON-PHI-PROCESSOR-7250-16GB-1_40-GHZ-68-CORE>TITLE=INTEL XEON PHI PROCESSOR 7250 (16GB, 1.40 GHZ, 68 CORE) PRODUCT SPECIFICATIONSWORK=INTEL ARK (PRODUCT SPECS), | SR2MD (B0) 68 (272) 1400 1600 34 MB 3046GFLOPSHTTPS://WWW.INTEL.COM/CONTENT/WWW/US/EN/PRODUCTS/PROCESSORS/XEON-PHI/XEON-PHI-PROCESSORS.HTML>TITLE=INTEL XEON PHI PROCESSORSACCESS-DATE=2017-02-25, 215 HJ8066702859200| SR2X1 (B0)ACCESS-DATE=2017-02-22, Intel ARK (Product Specs), | SR2X0 (B0)| 230| HJ8066702268900ACCESS-DATE=2017-02-22, Intel ARK (Product Specs), | SR2WY (B0) 72 (288) 1500 1700 36 MB 3456GFLOPS| 245| HJ8066702974700ACCESS-DATE=2017-02-22, Intel ARK (Product Specs), | SR2WZ (B0)| 260| HJ8066702975200

Knights Mill

Knights Mill is Intel's codename for a Xeon Phi product specialized in deep learning,NEWS, Smith, Ryan, Intel Announces Knight's Mill: A Xeon Phi for Deep Learning,weblink 17 August 2016, Anandtech, 17 August 2016, initially released in December 2017.NEWS, Cutress, Ian, Intel Lists Knights Mill Xeon Phi on ARK: Up to 72 cores at 320W with QFMA and VNNI,weblink 19 December 2017, Anandtech, 19 December 2017, Nearly identical in specifications to Knights Landing, Knights Mill includes optimizations for better utilization of AVX-512 instructions. Single-precision and variable-precision floating-point performance increased, at the expense of double-precision floating-point performance.

Models{| class="wikitable sortable"|+Models of Xeon Phi X205 CPU Series

! rowspan="2" | Xeon Phi72x5 Series! rowspan="2" |sSpec number! rowspan="2" | Cores(Threads)! colspan="2" | Clock (MHz)! rowspan="2" | L2cache! colspan="2" | MCDRAM memory! colspan="2" | DDR4 memory! rowspan="2" | Peak DPcompute! rowspan="2" | TDP(W)! rowspan="2" class="unsortable" | Socket! rowspan="2" class="unsortable" | Release date! rowspan="2" |Part number! class="unsortable" | Base! class="unsortable" | Turbo! class="unsortable" | Quantity! class="unsortable" | BW! class="unsortable" | Capacity! class="unsortable" | BW| Xeon Phi 7235|SR3VF (A0)| 64 (256)| 1300| 1400| 32 MB 16 GB 400+ GB/s 384 GB | 102.4 GB/s| {{TBA}}| 250 SVLCLGA3647 Q4 2017|HJ8068303823900| Xeon Phi 7255|SR3VG (A0)| 68 (272)| 1100| 1200| 34 MB| 115.2 GB/s| {{TBA}}| 215|HJ8068303826300| Xeon Phi 7285|SR3VE (A0)| 68 (272)| 1300| 1400| 34 MB| 115.2 GB/s| {{TBA}}| 250|HJ8068303823800| Xeon Phi 7295|SR3VD (A0)| 72 (288)| 1500| 1600| 36 MB| 115.2 GB/s| {{TBA}}| 320|HJ8068303823700

Knights Hill

Knights Hill was the codename for the third-generation MIC architecture, for which Intel announced the first details at SC14.SC14: Supercomputing '14; International Conference for High Performance Computing, Networking, Storage and Analysis in year 2014 It was to be manufactured in a 10 nm process.{{citation |author=Eric Gardner |title=What public disclosures has Intel made about Knights Landing? |date=25 November 2014 |url=https://software.intel.com/en-us/articles/what-disclosures-has-intel-made-about-knights-landing/ |publisher=Intel Corporation |archive-url=https://web.archive.org/web/20150223090350weblink |archive-date=23 February 2015 |url-status=dead}}Knights Hill was expected to be used in the United States Department of Energy Aurora supercomputer, to be deployed at Argonne National Laboratory.{{citation |author=ALCF staff |title=Introducing Aurora |date=9 April 2015 |url=https://www.alcf.anl.gov/articles/introducing-aurora}}{{citation |author=ALCF staff |title=Aurora |date=9 April 2015 |url=https://aurora.alcf.anl.gov/}} However, Aurora was delayed in favor of using an "advanced architecture" with a focus on machine learning.NEWS, Hemsoth, Nicole, 23 May 2017, Some Surprises in the 2018 DoE Budget for Supercomputing,weblink 13 November 2017, Next Platform, NEWS, Brueckner, Rich, 16 June 2017, Is Aurora Morphing into an Exascale AI Supercomputer?,weblink 13 November 2017, Inside HPC, In 2017, Intel announced that Knights Hill had been canceled in favor of another architecture built from the ground up to enable Exascale computing in the future. This new architecture is now expected for 2020–2021{{Update inline|date=January 2024|reason=The date of the event predicted near this tag has passed.}}.NEWS, Damkroger, Trish, 13 November 2017, Unleashing high performance computing today and tomorrow,weblink Intel IT Peer Network, NEWS, Kampman, Jeff, 13 November 2017, Intel quietly kills off next-gen Knights Hill Xeon Phi chips,weblink 13 November 2017, Tech Report,

Programming

One performance and programmability study reported that achieving high performance with Xeon Phi still needs help from programmers and that merely relying on compilers with traditional programming models is insufficient.CONFERENCE, Fang, Jianbin, Sips, Henk, Zhang, Lilun, Xu, Chuanfu, Yonggang, Che, Varbanescu, Ana Lucia, 2014, Test-Driving Intel Xeon Phi,weblink 2014 ACM/SPEC International Conference on Performance Engineering,weblink 11 November 2017, 30 December 2013, dead, Other studies in various domains, such as life sciences{{citation |arxiv= 1506.08612|title= Accelerating DNA Sequence Analysis using Intel Xeon Phi |date= 29 June 2015|bibcode= 2015arXiv150608612M|last1= Memeti |first1= Suejb |last2= Pllana |first2= Sabri |last3= Benkner |first3= Siegfried |last4= Pllana |first4= Sabri |last5= Sandrieser |first5= Martin |last6= Bachmayer |first6= Beverly }} and deep learning,{{citation |arxiv= 1506.09067|title= The Potential of the Intel Xeon Phi for Supervised Deep Learning |date= 30 June 2015|bibcode= 2015arXiv150609067V|last1= Viebke |first1= Andre |last2= Pllana |first2= Sabri |last3= Benkner |first3= Siegfried |last4= Pllana |first4= Sabri |last5= Sandrieser |first5= Martin |last6= Bachmayer |first6= Beverly }} have shown that exploiting the thread- and SIMD-parallelism of Xeon Phi achieves significant speed-ups.

Competitors

• Nvidia Tesla, a direct competitor in the HPC marketWEB,weblink Intel takes wraps off 50-core supercomputing processor plans, Jon Stokes, 20 June 2011, Ars Technica,
• AMD Radeon Pro and AMD Radeon Instinct direct competitors in the HPC market

See also

• Texas Advanced Computing Center{{snd}} "Stampede" supercomputer incorporates Xeon Phi chips.NEWS, Intel's Xeon Phi in 10 Petaflops supercomputer, Johan De Gelas, AnandTech,weblink 11 September 2012, 12 December 2012, Stampede is capable of 10 petaFLOPS.
• AVX-512
• Cell (microprocessor)
• Intel Tera-Scale
• Massively parallel
• Xeon

References

{{reflist}}

External links

{{commons category|Intel MIC}}

• Intel pages: Intel Xeon Phi Processors
• Chips and Cheese, December 8, 2022, Knight’s Landing: Atom with AVX-512

{{Intel processors}}