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{{Short description|Standardized way to automatically access information about a memory module}}{{Use dmy dates|date=March 2020}}In computing, serial presence detect (SPD) is a standardized way to automatically access information about a memory module. Earlier 72-pin SIMMs included five pins that provided five bits of parallel presence detect (PPD) data, but the 168-pin DIMM standard changed to a serial presence detect to encode more information.{{Citation |url=http://findarticles.com/p/articles/mi_m0EKF/is_n2153_v43/ai_19102210/ |title=Serial Presence Detection poised for limelight |author1=Thomas P. Koenig |author2=Nathan John |journal=Electronic News |date=1997-02-03 |volume=43 |issue=2153}}When an ordinary modern computer is turned on, it starts by doing a power-on self-test (POST). Since about the mid-1990s, this process includes automatically configuring the hardware currently present. SPD is a memory hardware feature that makes it possible for the computer to know what memory is present, and what memory timings to use to access the memory.Some computers adapt to hardware changes completely automatically. In most cases, there is a special optional procedure for accessing BIOS parameters, to view and potentially make changes in settings. It may be possible to control how the computer uses the memory SPD data—to choose settings, selectively modify memory timings, or possibly to completely override the SPD data (see overclocking).

Stored information

For a memory module to support SPD, the JEDEC standards require that certain parameters be in the lower 128 bytes of an EEPROM located on the memory module. These bytes contain timing parameters, manufacturer, serial number and other useful information about the module. Devices utilizing the memory automatically determine key parameters of the module by reading this information. For example, the SPD data on an SDRAM module might provide information about the CAS latency so the system can set this correctly without user intervention.The SPD EEPROM firmware is accessed using SMBus, a variant of the I2C protocol. This reduces the number of communication pins on the module to just two: a clock signal and a data signal. The EEPROM shares ground pins with the RAM, has its own power pin, and has three additional pins (SA0–2) to identify the slot, which are used to assign the EEPROM a unique address in the range 0x50–0x57. Not only can the communication lines be shared among 8 memory modules, the same SMBus is commonly used on motherboards for system health monitoring tasks such as reading power supply voltages, CPU temperatures, and fan speeds.SPD EEPROMs also respond to I2C addresses 0x30–0x37 if they have not been write protected, and an extension (TSE series) uses addresses 0x18–0x1F to access an optional on-chip temperature sensor. All those values are seven-bit I2C addresses formed by a Device Type Identifier Code prefix (DTIC) with SA0-2: to read (1100) from slot 3, one uses 110 0011 = 0x33. With a final R/W bit it forms the 8-bit Device Select Code.JEDEC Standard 21-C section 4.1.4 "Definition of the TSE2002av Serial Presence Detect (SPD) EEPROM with Temperature Sensor (TS) for Memory Module Applications" Note that the semantics of slot-id is different for write-protection operations: for them they can be not passed by the SA pins at all.WEB, TN-04-42: Memory Module Serial Presence-Detect Write Protection,weblink Micron, Before SPD, memory chips were spotted with parallel presence detect (PPD). PPD used a separate pin for each bit of information, which meant that only the speed and density of the memory module could be stored because of the limited space for pins.

SDR SDRAM

File:SPD SDRAM.jpg|thumb|Memory device on an SDRAMSDRAMThe first SPD specification was issued by JEDEC and tightened up by Intel as part of its PC100 memory specification introduced in 1998.WEB,weblink Ram Guide, Dean Kent, 24 October 1998, Tom's Hardware, WEB,weblink PC100 SDRAM: An Introduction, Anand Lal, Shimpi, www.anandtech.com, Application note INN-8668-APN3: SDRAM SPD Data Standards, memorytesters.com Most values specified are in binary-coded decimal form. The most significant nibble can contain values from 10 to 15, and in some cases extends higher. In such cases, the encodings for 1, 2 and 3 are instead used to encode 16, 17 and 18. A most significant nibble of 0 is reserved to represent "undefined".The SPD ROM defines up to three DRAM timings, for three CAS latencies specified by set bits in byte 18. First comes the highest CAS latency (fastest clock), then two lower CAS latencies with progressively lower clock speeds.{|class=wikitableurl=http://www.taricorp.net/wp-content/uploads/2012/04/SPDSDRAM1.2a1.pdf |title=PC SDRAM Serial Presence Detect (SPD) Specification |date=December 1997 |version=1.2A |page=28}}! colspan=2 | Byte! colspan=8 | Bit! rowspan=2 | Notes! (dec.) !! (hex.)! 7 !! 6 !! 5 !! 4 !! 3 !! 2 !! 1 !! 0

		Number of bytes present								Typically 128

		log2(size of SPD EEPROM)								Typically 8 (256 bytes)

		Basic memory type (4: SPD SDRAM)

		Bank 2 row address bits (0–15)				colspan=4	| Bank 2 is 0 if same as bank 1

		Bank 2 column address bits (0–15)				colspan=4	| Bank 2 is 0 if same as bank 1

		Number of RAM banks on module (1–255)								Commonly 1 or 2

		Module data width low byte								Commonly 64, or 72 for ECC DIMMs

		Module data width high byte								0, unless width ≥ 256 bits

		Interface voltage level of this assembly (not the same as Vcc supply voltage) (0–4)								Decoded by table lookup

		Nanoseconds (0–15)				colspan=4	| Clock cycle time at highest CAS latency

		Nanoseconds (0–15)				colspan=4	| SDRAM access time from clock (tAC)

		DIMM configuration type (0–2): non-ECC, parity, ECC								Table lookup

			Refresh period (0–5): 64, 256, 128, 32, 16, 8 kHz							Refresh requirements

			Bank 1 primary SDRAM width (1–127, usually 8)							Width of bank 1 data SDRAM devices. Bank 2 may be same width, or 2× width if bit 7 is set.

			Bank 1 ECC SDRAM width (0–127)							Width of bank 1 ECC/parity SDRAM devices. Bank 2 may be same width, or 2× width if bit 7 is set.

		Clock delay for random column reads								Typically 1

									| Burst lengths supported (bitmap)

		Banks per SDRAM device (1–255)								Typically 2 or 4

										CAS}} latencies supported (bitmap)

										CS}} latencies supported (bitmap)

										WE}} latencies supported (bitmap)

									| Memory module feature bitmap

									RAS}} precharge	Memory chip feature support bitmap

		Nanoseconds (4–18)				colspan=4	| Clock cycle time at medium CAS latency

		Nanoseconds (4–18)				colspan=4	| Data access time from clock (tAC)

		Nanoseconds (1–63)						colspan=2	| Clock cycle time at short CAS latency.

		Nanoseconds (1–63)						colspan=2	| Data access time from clock (tAC)

		Nanoseconds (1–255)								Minimum row precharge time (tRP)

		Nanoseconds (1–255)								Minimum row active–row active delay (tRRD)

		Nanoseconds (1–255)								Minimum {{overline	CAS}} delay (tRCD)

		Nanoseconds (1–255)								Minimum active to precharge time (tRAS)

									| Module bank density (bitmap). Two bits set if different size banks.

			Nanoseconds (0–7)			colspan=4	| Address/command setup time from clock

			Nanoseconds (0–7)			colspan=4	| Address/command hold time after clock

			Nanoseconds (0–7)			colspan=4	| Data input setup time from clock

			Nanoseconds (0–7)			colspan=4	| Data input hold time after clock

| 0x24–0x3d	Reserved}}| For future standardization

		Major revision (0–9)				colspan=4	| SPD revision level; e.g., 1.2

		Checksum								Sum of bytes 0–62, not then negated

		Manufacturer JEDEC id.								Stored little-endian, trailing zero-padded

		Module manufacturing location								Vendor-specific code

		Module part number								ASCII, space-padded

		Module revision code								Vendor-specific code

		Tens of years (0–9: 0–90)				colspan=4		Manufacturing date (YYWW)

		Tens of weeks (0–5: 0–50)				colspan=4| Weeks (0–9)

		Module serial number								Vendor-specific code

		Manufacturer-specific data								Could be enhanced performance profile

		0x66{{sic}} for 66 MHz, 0x64 for 100 MHz								Intel frequency support

									| Intel feature bitmap

DDR SDRAM

The DDR DIMM SPD format is an extension of the SDR SDRAM format. Mostly, parameter ranges are rescaled to accommodate higher speeds.{|class=wikitable|+ SPD contents for DDR SDRAM! colspan=2 | Byte! colspan=8 | Bit! rowspan=2 | Notes! (dec.) !! (hex.)! 7 !! 6 !! 5 !! 4 !! 3 !! 2 !! 1 !! 0

		Number of bytes written								Typically 128

		log2(size of SPD EEPROM)								Typically 8 (256 bytes)

		Basic memory type (7 = DDR SDRAM)

		Bank 2 row address bits (0–15)				colspan=4	| Bank 2 is 0 if same as bank 1.

		Bank 2 column address bits (0–15)				colspan=4	| Bank 2 is 0 if same as bank 1.

		Number of RAM banks on module (1–255)								Commonly 1 or 2

		Module data width low byte								Commonly 64, or 72 for ECC DIMMs

		Module data width high byte								0, unless width ≥ 256 bits

		Interface voltage level of this assembly (not the same as Vcc supply voltage) (0–5)								Decoded by table lookup

		Nanoseconds (0–15)				colspan=4	| Clock cycle time at highest CAS latency.

		Tenths of nanoseconds (0.0–0.9)				colspan=4	| SDRAM access time from clock (tAC)

		DIMM configuration type (0–2): non-ECC, parity, ECC								Table lookup

			Refresh period (0–5): 64, 256, 128, 32, 16, 8 kHz							Refresh requirements

			Bank 1 primary SDRAM width (1–127)							Width of bank 1 data SDRAM devices. Bank 2 may be same width, or 2× width if bit 7 is set.

			Bank 1 ECC SDRAM width (0–127)							Width of bank 1 ECC/parity SDRAM devices. Bank 2 may be same width, or 2× width if bit 7 is set.

		Clock delay for random column reads								Typically 1

									| Burst lengths supported (bitmap)

		Banks per SDRAM device (1–255)								Typically 4

										CAS}} latencies supported (bitmap)

										CS}} latencies supported (bitmap)

										WE}} latencies supported (bitmap)

									| Memory module feature bitmap

									| Memory chip feature bitmap

		Nanoseconds (0–15)				colspan=4	| Clock cycle time at medium CAS latency.

		Tenths of nanoseconds (0.0–0.9)				colspan=4	| Data access time from clock (tAC)

		Nanoseconds (0–15)				colspan=4	| Clock cycle time at short CAS latency.

		Tenths of nanoseconds (0.0–0.9)				colspan=4	| Data access time from clock (tAC)

		Nanoseconds (1–63)						colspan=2	| Minimum row precharge time (tRP)

		Nanoseconds (1–63)						colspan=2	| Minimum row active–row active delay (tRRD)

		Nanoseconds (1–63)						colspan=2		RAS}} to {{overline|CAS}} delay (tRCD)

		Nanoseconds (1–255)								Minimum active to precharge time (tRAS)

									| Module bank density (bitmap). Two bits set if different size banks.

		Tenths of nanoseconds (0.0–0.9)				colspan=4	| Address/command setup time from clock

		Tenths of nanoseconds (0.0–0.9)				colspan=4	| Address/command hold time after clock

		Tenths of nanoseconds (0.0–0.9)				colspan=4	| Data input setup time from clock

		Tenths of nanoseconds (0.0–0.9)				colspan=4	| Data input hold time after clock

| 36–40

	Reserved}}| Superset information

		Nanoseconds (1–255)								Minimum active to active/refresh time (tRC)

		Nanoseconds (1–255)								Minimum refresh to active/refresh time (tRFC)

		Nanoseconds (1–63, or 255: no maximum)						colspan=2	| Maximum clock cycle time (tCK max.)

		Hundredths of nanoseconds (0.01–2.55)								Maximum skew, DQS to any DQ. (tDQSQ max.)

		Tenths of nanoseconds (0.0–1.2)				colspan=4	| Read data hold skew factor (tQHS)

| 0x2e	Reserved}}| For future standardization

		—						colspan=2	| Height of DIMM module, table lookup

| 0x30–0x3d	Reserved}}| For future standardization

		Major revision (0–9)				colspan=4	| SPD revision level, 0.0 or 1.0

		Checksum								Sum of bytes 0–62, not then negated

		Manufacturer JEDEC id.								Stored little-endian, trailing zero-padded

		Module manufacturing location								Vendor-specific code

		Module part number								ASCII, space-padded

		Module revision code								Vendor-specific code

		Tens of years (0–90)				colspan=4		Manufacturing date (YYWW)

		Tens of weeks (0–50)				colspan=4| Weeks (0–9)

		Module serial number								Vendor-specific code

		Manufacturer-specific data								Could be enhanced performance profile

DDR2 SDRAM

The DDR2 SPD standard makes a number of changes, but is roughly similar to the above. One notable deletion is the confusing and little-used support for DIMMs with two ranks of different sizes.For cycle time fields (bytes 9, 23, 25 and 49), which are encoded in BCD, some additional encodings are defined for the tenths digit to represent some common timings exactly:{|class=wikitable|+ DDR2 BCD extensions! Hex !! Binary !! Significance

		1|4}})

		1|3}})

		2|3}})

		3|4}})

		7|8}}, Nvidia XMP extension)

		Reserved}}

{|class=wikitable|+ SPD contents for DDR2 SDRAM! colspan=2 | Byte! colspan=8 | Bit! rowspan=2 | Notes! Dec !! Hex !! 7 !! 6 !! 5 !! 4 !! 3 !! 2 !! 1 !! 0

		Number of bytes written								Typically 128

		log2(size of SPD EEPROM)								Typically 8 (256 bytes)

		Basic memory type (8 = DDR2 SDRAM)

		Reserved}}				colspan=4	|

		Reserved}}				colspan=4	|

		Vertical height			Stack?	ConC?	colspan=3	| Commonly 0 or 1, meaning 1 or 2

		Module data width								Commonly 64, or 72 for ECC DIMMs

		Reserved}}

		Interface voltage level of this assembly (not the same as Vcc supply voltage) (0–5)								Decoded by table lookup.Commonly 5 = SSTL 1.8 V

		Nanoseconds (0–15)				colspan=4	| Clock cycle time at highest CAS latency.

		Tenths of nanoseconds (0.0–0.9)				colspan=4	| SDRAM access time from clock (tAC)

		DIMM configuration type (0–2): non-ECC, parity, ECC								Table lookup

			Refresh period (0–5): 64, 256, 128, 32, 16, 8 kHz							Refresh requirements

		Primary SDRAM width (1–255)								Commonly 8 (module built from ×8 parts) or 16

		ECC SDRAM width (0–255)								Width of bank ECC/parity SDRAM devices. Commonly 0 or 8.

		Reserved}}

		—	—	—	—	8	4	—	—	Burst lengths supported (bitmap)

		Banks per SDRAM device (1–255)								Typically 4 or 8

										CAS}} latencies supported (bitmap)

		Reserved}}

									| DIMM type of this assembly (bitmap)

									| Memory module feature bitmap

									| Memory chip feature bitmap

		Nanoseconds (0–15)				colspan=4	| Clock cycle time at medium CAS latency.

		Tenths of nanoseconds (0.0–0.9)				colspan=4	| Data access time from clock (tAC)

		Nanoseconds (0–15)				colspan=4	| Clock cycle time at short CAS latency.

		Tenths of nanoseconds (0.0–0.9)				colspan=4	| Data access time from clock (tAC)

		Nanoseconds (1–63)						colspan=2	| Minimum row precharge time (tRP)

		Nanoseconds (1–63)						colspan=2	| Minimum row active–row active delay (tRRD)

		Nanoseconds (1–63)						colspan=2		RAS}} to {{overline|CAS}} delay (tRCD)

		Nanoseconds (1–255)								Minimum active to precharge time (tRAS)

									| Size of each rank (bitmap).

		Tenths of nanoseconds (0.0–1.2)				colspan=4	| Address/command setup time from clock

		Tenths of nanoseconds (0.0–1.2)				colspan=4	| Address/command hold time after clock

		Tenths of nanoseconds (0.0–0.9)				colspan=4	| Data input setup time from strobe

		Tenths of nanoseconds (0.0–0.9)				colspan=4	| Data input hold time after strobe

		Nanoseconds (1–63)						colspan=2	| Minimum write recovery time (tWR)

		Nanoseconds (1–63)						colspan=2	| Internal write to read command delay (tWTR)

		Nanoseconds (1–63)						colspan=2	| Internal read to precharge command delay (tRTP)

		Reserved}}								Reserved for "memory analysis probe characteristics"

			tRC fractional ns (0–5):0, 0.25, 0.33, 0.5, 0.66, 0.75			colspan=3		| Extension of bytes 41 and 42.

		Nanoseconds (1–255)								Minimum active to active/refresh time (tRC)

		Nanoseconds (1–255)								Minimum refresh to active/refresh time (tRFC)

		Nanoseconds (0–15)				colspan=4	| Maximum clock cycle time (tCK max)

		Hundredths of nanoseconds (0.01–2.55)								Maximum skew, DQS to any DQ. (tDQSQ max)

		Hundredths of nanoseconds (0.01–2.55)								Read data hold skew factor (tQHS)

		Microseconds (1–255)								PLL relock time

		Reserved}}								For future standardization.

		Major revision (0–9)				colspan=4	| SPD revision level, usually 1.0

		Checksum								Sum of bytes 0–62, not negated

		Manufacturer JEDEC ID								Stored little-endian, trailing zero-pad

		Module manufacturing location								Vendor-specific code

		Module part number								ASCII, space-padded (limited to (,-,), A–Z, a–z, 0–9, space)

		Module revision code								Vendor-specific code

		Years since 2000 (0–255)								rowspan=2| Manufacturing date (YYWW)

		Weeks (1–52)

		Module serial number								Vendor-specific code

		Manufacturer-specific data								Could be enhanced performance profile

DDR3 SDRAM

The DDR3 SDRAM standard significantly overhauls and simplifies the SPD contents layout. Instead of a number of BCD-encoded nanosecond fields, some "timebase" units are specified to high precision, and various timing parameters are encoded as multiples of that base unit.WEB,weblink Understanding DDR3 Serial Presence Detect (SPD) Table, Further, the practice of specifying different time values depending on the CAS latency has been dropped; now there are just a single set of timing parameters.Revision 1.1 lets some parameters be expressed as a "medium time base" value plus a (signed, −128 +127) "fine time base" correction. Generally, the medium time base is 1/8 ns (125 ps), and the fine time base is 1, 2.5 or 5 ps. For compatibility with earlier versions that lack the correction, the medium time base number is usually rounded up and the correction is negative. Values that work this way are:{|class=wikitable|+ DDR3 SPD two-part timing parameters! MTB byte || FTB byte || Value

	| tCKmin, minimum clock period

	| tAAmin, minimum CAS latency time

	| tRCDmin, minimum RAS# to CAS# delay

	| tRPmin, minimum row precharge delay

	| tRCmin, minimum active to active/precharge delay

{|class=wikitable|+ SPD contents for DDR3 SDRAMJESD21-C Annex K: Serial Presence Detect for DDR3 SDRAM Modules, Release 4, SPD Revision 1.1JESD21-C Annex K: Serial Presence Detect for DDR3 SDRAM Modules, Release 6, SPD Revision 1.3! colspan=2 | Byte! colspan=8 | Bit! rowspan=2 | Notes! Dec !! Hex !! 7 !! 6 !! 5 !! 4 !! 3 !! 2 !! 1 !! 0

			SPD bytes total (undef/256)			colspan=4	|

		SPD major revision				colspan=4	|1.0, 1.1, 1.2 or 1.3

		Basic memory type (11 = DDR3 SDRAM)								Type of RAM chips

		Reserved}}				colspan=4	| Type of module; e.g., 2 = Unbuffered DIMM, 3 = SO-DIMM, 11=LRDIMM

			Bank address bits−3			colspan=4	| Zero means 8 banks, 256 Mibit.

				Row address bits−12			colspan=3	|

		Reserved}}					1.25 V	1.35 V	Not 1.5 V	Modules voltages supported. 1.5 V is default.

				ranks−1			colspan=3	| Module organization

					ECC bits (001=8)		colspan=3	| 0x03 for 64-bit, non-ECC DIMM.

		Dividend, picoseconds (1–15)				colspan=4	| Fine Time Base, dividend/divisor

		Dividend, nanoseconds (1–255)								rowspan=2| Medium Time Base, dividend/divisor; commonly 1/8

		Divisor, nanoseconds (1–255)

		Minimum cycle time tCKmin								In multiples of MTB

		Reserved}}

										CAS latencies supported (bitmap)

								| 12

		Minimum CAS latency time, tAAmin								In multiples of MTB; e.g., 80/8 ns.

		Minimum write recovery time, tWRmin								In multiples of MTB; e.g., 120/8 ns.

		Minimum RAS to CAS delay time, tRCDmin								In multiples of MTB; e.g., 100/8 ns.

		Minimum row to row active delay time, tRRDmin								In multiples of MTB; e.g., 60/8 ns.

		Minimum row precharge time, tRPmin								In multiples of MTB; e.g., 100/8 ns.

		tRCmin, bits 11:8				colspan=4	| Upper 4 bits of bytes 23 and 22

		Minimum active to time, tRASmin, bits 7:0								In multiples of MTB; e.g., 280/8 ns.

		Minimum active to active/refresh, tRCmin, bits 7:0								In multiples of MTB; e.g., 396/8 ns.

		Minimum refresh recovery delay, tRFCmin, bits 7:0								rowspan=2| In multiples of MTB; e.g., 1280/8 ns.

		Minimum refresh recovery delay, tRFCmin, bits 15:8

		Minimum internal write to read delay, tWTRmin								In multiples of MTB; e.g., 60/8 ns.

		Minimum internal read to precharge delay, tRTPmin								In multiples of MTB; e.g., 60/8 ns.

		Reserved}}				colspan=4		In multiples of MTB; e.g., 240/8 ns.

		Minimum four activate window delay tFAWmin, bits 7:0

									| SDRAM optional features support bitmap

									| SDRAM thermal and refresh options

			Accuracy (TBD; currently 0 = undefined)							DIMM thermal sensor present?

			Die count			colspan=2 {{n/a}}	colspan=2	| Nonstandard SDRAM device type (e.g., stacked die)

		tCKmin correction (new for 1.1)								Signed multiple of FTB, added to byte 12

		tAAmin correction (new for 1.1)								Signed multiple of FTB, added to byte 16

		tRCDmin correction (new for 1.1)								Signed multiple of FTB, added to byte 18

		tRPmin correction (new for 1.1)								Signed multiple of FTB, added to byte 20

		tRCmin correction (new for 1.1)								Signed multiple of FTB, added to byte 23

		Reserved}}								For future standardization.

		Vendor specific		colspan=2		Maximum Activate Count (MAC) (untested/700k/600k/.../200k/reserved/∞)				For row hammer mitigation

		Reserved}}								For future standardization.

					Module height, mm (1–31, >45)					Module nominal height

		Back thickness, mm (1–16)				colspan=4	| Module thickness, value = ceil(mm) − 1

			Revision		colspan=5	| JEDEC reference design used (11111=none)

		Module-specific section								Differs between registered/unbuffered

		Module manufacturer ID, lsbyte								rowspan=2| Assigned by JEP-106

		Module manufacturer ID, msbyte

		Module manufacturing location								Vendor-specific code

		Tens of years				colspan=4	| Manufacturing year (BCD)

		Tens of weeks				colspan=4	| Manufacturing week (BCD)

		Module serial number								Vendor-specific code

		SPD CRC-16								Includes bytes 0–116 or 0–125; see byte 0 bit 7

		Module part number								ASCII subset, space-padded

		Module revision code								Vendor-defined

		DRAM manufacturer ID								As distinct from module manufacturer

		Manufacturer-specific data

		Available for customer use

The memory capacity of a module can be computed from bytes 4, 7 and 8. The module width (byte 8) divided by the number of bits per chip (byte 7) gives the number of chips per rank. That can then be multiplied by the per-chip capacity (byte 4) and the number of ranks of chips on the module (usually 1 or 2, from byte 7).

DDR4 SDRAM

The DDR4 SDRAM "Annex L" standard for SPD changes the EEPROM module used. Instead of the old AT24C02-compatible 256-byte EEPROMs, JEDEC now defines a new nonstandard EE1004 type with two pages at the SMBus level each with 256 bytes. The new memory still uses the old 0x50–0x57 addresses, but two additional address at 0x36 (SPA0) and 0x37 (SPA1) are now used to receive commands to select the currently-active page for the bus, a form of bank switching.WEB, Delvare, Jean, [PATCH] eeprom: New ee1004 driver for DDR4 memory,weblink LKML, 7 November 2019, Internally each logical page is further divided into two physical blocks of 128 bytes each, totaling four blocks and 512 bytes.WEB, JEDEC, Annex L: Serial Presence Detect (SPD) for DDR4 SDRAM Modules,weblink Other semantics for "special" address ranges remain the same, although write protection is now addressed by blocks and a high voltage at SA0 is now required to change its status.WEB, JEDEC, EE1004 and TSE2004 Device Specification (Draft),weblink 7 November 2019, Annex L defines a few different layouts that can be plugged into a 512-byte (of which a maximum of 320 bytes are defined) template, depending on the type of the memory module. The bit definitions are similar to DDR3.{|class=wikitable|+ SPD contents for DDR4 SDRAMJESD21-C Annex L: Serial Presence Detect for DDR4 SDRAM Modules, Release 5! colspan=2 | Byte! colspan=8 | Bit! rowspan=2 | Notes! Dec !! Hex !! 7 !! 6 !! 5 !! 4 !! 3 !! 2 !! 1 !! 0

		SPD bytes used

		SPD revision n								Typically 0x10, 0x11, 0x12

		Basic memory type (12 = DDR4 SDRAM)								Type of RAM chips

		Reserved}}				colspan=4	| Type of module; e.g., 2 = Unbuffered DIMM, 3 = SO-DIMM, 11=LRDIMM

		Bank group bits		colspan=2		Total SDRAM capacity per die in megabits				Zero means no bank groups, 4 banks, 256 Mibit.

		Reserved}}		colspan=3		Column address bits−9

			Die count			colspan=2 {{n/a		Signal loading

		Reserved}}		colspan=2		Maximum activate count (MAC)				SDRAM optional features

		Reserved}}								SDRAM thermal and refresh options

		Post package repair (PPR)		Soft PPR	colspan=5 {{n/a	| Other SDRAM optional features

			Die count−1			colspan=2		Signal loading		Secondary SDRAM package type

		Reserved}}						Endurant flag	Operable flag	Module nominal voltage, VDD

		Reserved}}	Rank mix	colspan=3		SDRAM device width			Module organization

		Reserved}}			colspan=2		Primary bus width			Module memory bus width in bits

			Reserved}}							Module thermal sensor

		Reserved}}				colspan=4|Extended base module type

		Reserved}}

		Reserved}}				colspan=2		Fine timebase (FTB)		Measured in ps.

		Minimum SDRAM cycle time, tCKAVGmin								In multiples of MTB; e.g., 100/8 ns.

		Maximum SDRAM cycle time, tCKAVGmax								In multiples of MTB; e.g., 60/8 ns.

									| CAS latencies supported bit-mask

									| CAS latencies supported bit-mask

									| CAS latencies supported bit-mask

			Reserved}}	36	35	34	33	32	31	CAS latencies supported bit-mask

		Minimum CAS latency time, tAAmin								In multiples of MTB; e.g., 1280/8 ns.

		Minimum RAS to CAS delay time, tRCDmin								In multiples of MTB; e.g., 60/8 ns.

		Minimum row precharge delay time, tRPmin								In multiples of MTB; e.g., 60/8 ns.

		Upper nibbles for tRASmin and tRCmin

		Minimum active to precharge delay time, tRASmin least significant byte								In multiples of MTB

		Minimum active to active/refresh delay time, tRCmin least significant byte								In multiples of MTB

		Minimum refresh recovery delay time, tRFC1min least significant byte								In multiples of MTB

		Minimum refresh recovery delay time, tRFC1min most significant byte								In multiples of MTB

		Minimum refresh recovery delay time, tRFC2min least significant byte								In multiples of MTB

		Minimum refresh recovery delay time, tRFC2min most significant byte								In multiples of MTB

		Minimum refresh recovery delay time, tRFC4min least significant byte								In multiples of MTB

		Minimum refresh recovery delay time, tRFC4min most significant byte								In multiples of MTB

		Reserved}}				colspan=4| tFAWmin most significant nibble

		Minimum four activate window delay time, tFAWmin least significant byte								In multiples of MTB

		Minimum activate to activate delay time, tRRD_Smin, different bank group								In multiples of MTB

		Minimum activate to activate delay time, tRRD_Lmin, same bank group								In multiples of MTB

		Minimum CAS to CAS delay time, tCCD_Lmin, same bank group								In multiples of MTB

		Upper nibble for tWRmin

		Minimum write recovery time, tWRmin								In multiples of MTB

		Upper nibbles for tWTRmin

		Minimum write to read time, tWTR_Smin, different bank group								In multiples of MTB

		Minimum write to read time, tWTR_Lmin, same bank group								In multiples of MTB

		Reserved}}								Base configuration section

		Connector to SDRAM bit mapping

		Reserved}}								Base configuration section

		Fine offset for minimum CAS to CAS delay time, tCCD_Lmin, same bank								Two's complement multiplier for FTB units

		Fine offset for minimum activate to activate delay time, tRRD_Lmin, same bank group								Two's complement multiplier for FTB units

		Fine offset for minimum activate to activate delay time, tRRD_Smin, different bank group								Two's complement multiplier for FTB units

		Fine offset for minimum active to active/refresh delay time, tRCmin								Two's complement multiplier for FTB units

		Fine offset for minimum row precharge delay time, tRPmin								Two's complement multiplier for FTB units

		Fine offset for minimum RAS to CAS delay time, tRCDmin								Two's complement multiplier for FTB units

		Fine offset for minimum CAS latency time, tAAmin								Two's complement multiplier for FTB units

		Fine offset for SDRAM maximum cycle time, tCKAVGmax								Two's complement multiplier for FTB units

		Fine offset for SDRAM minimum cycle time, tCKAVGmin								Two's complement multiplier for FTB units

		Cyclic rendundancy code (CRC) for base config section, least significant byte								CRC16 algorithm

		Cyclic rendundancy code (CRC) for base config section, most significant byte								CRC16 algorithm

		Module-specific section								Dependent upon memory module family (UDIMM, RDIMM, LRDIMM)

		Hybrid memory architecture specific parameters

		Extended function parameter block

		Module manufacturer								See JEP-106

		Module manufacturing location								Manufacturer-defined manufacturing location code

		Module manufacturing year								Represented in Binary Coded Decimal (BCD)

		Module manufacturing week								Represented in Binary Coded Decimal (BCD)

		Module serial number								Manufacturer-defined format for a unique serial number across part numbers

		Module part number								ASCII part number, unused digits should be set to 0x20

		Module revision code								Manufacturer-defined revision code

		DRAM manufacturer ID code								See JEP-106

		DRAM stepping								Manufacturer-defined stepping or 0xFF if not used

		Manufacturer's specific data

		Reserved}}

DDR5 SDRAM

Preliminary table for DDR5, based on JESD400-5 specification.WEB, 2023, JESD400-5B(JESD400-5B),weblink 31 December 2023, jedec, DDR5 expands the SPD table to 1024-byte. SPD of DDR5 is using the I3C bus.{|class=wikitable|+ SPD contents for DDR5 SDRAM! colspan=2 | Byte! colspan=8 | Bit! rowspan=2 | Notes! Dec !! Hex !! 7 !! 6 !! 5 !! 4 !! 3 !! 2 !! 1 !! 0

		Number of bytes in SPD device

		SPD revision for base configuration parameters

		Key byte / host bus command protocol type

		Key byte / module type

		First SDRAM density and package

		First SDRAM addressing

		First SDRAM I/O width

		First SDRAM bank groups & banks per bank group

		Second SDRAM density and package

		Second SDRAM addressing

		Second SDRAM I/O width

		Second SDRAM bank groups & banks per bank group

		SDRAM optional features

		Thermal and refresh options

		Reserved}}

		Reserved}}

		SDRAM nominal voltage, VDD

Extensions

The JEDEC standard only specifies some of the SPD bytes. The truly critical data fits into the first 64 bytes,JEDEC Standard 21-C section 4.1.2.4 "SPDs for DDR SDRAM"JEDEC Standard 21-C section 4.1.2.10 "Specific SPDs for DDR2 SDRAM"JEDEC Standard 21-C section 4.1.2.11 "Serial Presence Detect (SPD) for DDR3 SDRAM Modules"JEDEC Standard 21-C section 4.1.2 "SERIAL PRESENCE DETECT STANDARD, General Standard"JEDEC Standard 21-C section 4.1.2.5 "Specific PDs for Synchronous DRAM (SDRAM)" while some of the remainder is earmarked for manufacturer identification. However, a 256-byte EEPROM is generally provided. A number of uses have been made of the remaining space.

Enhanced Performance Profiles (EPP)

Memory generally comes with conservative timing recommendations in the SPD ROM, to ensure basic functionality on all systems. Enthusiasts often spend considerable time manually adjusting the memory timings for higher speed.Enhanced Performance Profiles is an extension of SPD, developed by Nvidia and Corsair, which includes additional information for higher-performance operation of DDR2 SDRAM, including supply voltages and command timing information not included in the JEDEC SPD spec. The EPP information is stored in the same EEPROM, but in bytes 99–127, which are unused by standard DDR2 SPD.{{Citation |url=http://www.nvidia.com/content/epp/epp_specifications.pdf |title=DDR2 UDIMM Enhanced Performance Profiles Design Specification |publisher=Nvidia |date=2006-05-12 |accessdate=2009-05-05}}{|class=wikitable|+ EPP SPD ROM usage! Bytes !! Size !! Full profiles !! Abbreviated profiles

		EPP header

		Profile FP1	Profile AP1

	| Profile AP2

		Profile FP2	Profile AP3

	| Profile AP4

The parameters are particularly designed to fit the memory controller on the nForce 5, nForce 6 and nForce 7 chipsets. Nvidia encourages support for EPP in the BIOS for its high-end motherboard chipsets. This is intended to provide "one-click overclocking" to get better performance with minimal effort.Nvidia's name for EPP memory that has been qualified for performance and stability is "SLI-ready memory"weblink {{Bare URL PDF|date=March 2022}} The term "SLI-ready-memory" has caused some confusion, as it has nothing to do with SLI video. One can use EPP/SLI memory with a single video card (even a non-Nvidia card), and one can run a multi-card SLI video setup without EPP/SLI memory.An extended version, EPP 2.0, supports DDR3 memory as well.Enhanced Performance Profiles 2.0 (pp. 2–3)

{{Anchor|XMP}}Intel Extreme Memory Profile (XMP)

A similar, Intel-developed JEDEC SPD extension was developed for DDR3 SDRAM DIMMs, later used in DDR4 SDRAM as well. XMP uses bytes 176–255, which are unallocated by JEDEC, to encode higher-performance memory timings.WEB, What Is Intel Extreme Memory Profile (Intel XMP)?,weblink Intel, September 26, 2022, Later, AMD developed AMP, an equivalent technology to XMP, for use in its "Radeon Memory" line of memory modules optimized for use in AMD platforms.WEB, Memory Profile Technology - AMP up your RAM,weblink AMD, 2012, January 8, 2018, WEB, Martin, Ryan, July 23, 2012, AMD introduces its XMP-equivalent AMP - eTeknix,weblink eTeknix, January 8, 2018, Furthermore, motherboard developers implemented their own technologies to allow their AMD-based motherboards to read XMP profiles: MSI offers A-XMP,WEB, MSI is worlds first brand to enable A-XMP on Ryzen for best DDR4 performance, launches new models,weblink MSI, March 21, 2017, January 8, 2018, ASUS has DOCP (Direct Over Clock Profile), and Gigabyte has EOCP (Extended Over Clock Profile).WEB, Tradesman1, What does XMP, DOCP, EOCP mean - Solved - Memory,weblink Tom's Hardware Forums, August 26, 2016, January 8, 2018, {|class=wikitableweblinkweblink" title="web.archive.org/web/20120306230940weblink">weblink Intel, March 6, 2012, October 2007, May 25, 2010, ! DDR3 Bytes !! Size !! Use

	| XMP header

	| XMP profile 1 ("enthusiast" settings)

	| XMP profile 2 ("extreme" settings)

The header contains the following data. Most importantly, it contains a "medium timebase" value MTB, as a rational number of nanoseconds (common values are 1/8, 1/12 and 1/16 ns). Many other later timing values are expressed as an integer number of MTB units.Also included in the header is the number of DIMMs per memory channel that the profile is designed to support; including more DIMMs may not work well.{|class="wikitable"|+ XMP Header bytes! DDR3 Byte !! Bits !! Use

		Magic number (programming)>magic number byte 1 0x0C

	| XMP magic number byte 2 0x4A

178	0	Profile 1 enabled (if 0, disabled)

| Profile 2 enabled

| Profile 1 DIMMs per channel (1–4 encoded as 0–3)

| Profile 2 DIMMs per channel

	Reserved}}

179	3:0	XMP minor version number (x.0 or x.1)

| XMP major version number (0.x or 1.x)

	| Medium timebase dividend for profile 1

	| Medium timebase divisor for profile 1 (MTB = dividend/divisor ns)

	| Medium timebase dividend for profile 2 (e.g. 8)

	| Medium timebase divisor for profile 2 (e.g. 1, giving MTB = 1/8 ns)

		Reserved}}

{|class="wikitable"|+ XMP profile bytes! DDR3 Byte 1 !! DDR3 Byte 2 !! Bits !! Use

185	rowspan=4		| Module Vdd voltage twentieths (0.00 or 0.05)

| Module Vdd voltage tenths (0.0–0.9)

| Module Vdd voltage units (0–2)

	Reserved}}

		| Minimum SDRAM clock period tCKmin (MTB units)

		| Minimum CAS latency time tAAmin (MTB units)

		| CAS latencies supported (bitmap, 4–11 encoded as bits 0–7)

189	rowspan=2		| CAS latencies supported (bitmap, 12–18 encoded as bits 0–6)

	Reserved}}

		| Minimum CAS write latency time tCWLmin (MTB units)

		| Minimum row precharge delay time tRPmin (MTB units)

		| Minimum RAS to CAS delay time tRCDmin (MTB units)

		| Minimum write recovery time tWRmin (MTB units)

194	rowspan=2		| tRASmin upper nibble (bits 11:8)

| tRCmin upper nibble (bits 11:8)

		| Minimum active to precharge delay time tRASmin bits 7:0 (MTB units)

		| Minimum active to active/refresh delay time tRCmin bits 7:0 (MTB units)

		| Maximum average refresh interval tREFI lsbyte (MTB units)

		| Maximum average refresh interval tREFI msbyte (MTB units)

		| Minimum refresh recovery delay time tRFCmin lsbyte (MTB units)

		| Minimum refresh recovery delay time tRFCmin msbyte (MTB units)

		| Minimum internal read to precharge command delay time tRTPmin (MTB units)

		| Minimum row active to row active delay time tRRDmin (MTB units)

203	rowspan=2		| tFAWmin upper nibble (bits 11:8)

	Reserved}}

		| Minimum four activate window delay time tFAWmin bits 7:0 (MTB units)

		| Minimum internal write to read command delay time tWTRmin (MTB units)

206	rowspan=4		| Write to read command turnaround time adjustment (0–7 clock cycles)

| Write to read command turnaround adjustment sign (0=pull-in, 1=push-out)

| Read to write command turnaround time adjustment (0–7 clock cycles)

| Read to write command turnaround adjustment sign (0=pull-in, 1=push-out)

207	rowspan=3		| Back-to-back command turnaround time adjustment (0–7 clock cycles)

| Back-to-back turnaround adjustment sign (0=pull-in, 1=push-out)

	Reserved}}

		| System CMD rate mode. 0=JTAG default, otherwise in peculiar units of MTB × tCK/ns.E.g. if MTB is 1/8 ns, then this is in units of 1/8 clock cycle.

			TBD).

			Reserved}}

		| Reserved, vendor-specific personality code.

All data above are for DDR3 (XMP 1.1); DDR4 specs are not yet available.

{{Anchor|EXPO}}AMD Extended Profiles for Overclocking (EXPO)

AMD's Extended Profiles for Overclocking (EXPO) is a JEDEC SPD extension developed for DDR5 DIMMs to apply a one-click automatic overclocking profile to system memory.WEB, AMD Extended Profiles for Overclocking,weblink AMD, September 26, 2022, WEB, Roach, Jacob, September 6, 2022, What is AMD EXPO and should my DDR5 have it?,weblink Digital Trends, September 26, 2022, AMD EXPO-certified DIMMs include optimised timings that optimise the performance of its Zen 4 processors.WEB, Bonshor, Gavin, August 30, 2022, AMD EXPO Memory Technology: One Click Overclocking Profiles For Ryzen 7000,weblink AnandTech, September 26, 2022, Unlike Intel's closed standard XMP, the EXPO standard is open and royalty-free. It can be used on Intel platforms. At launch in September 2022, there are 15 partner RAM kits with EXPO-certification available reaching up to 6400 MT/s.WEB, AMD announces EXPO technology for DDR5 memory overclocking,weblink VideoCardz, August 30, 2022, September 26, 2022,

Vendor-specific memory

A common misuse is to write information to certain memory regions to bind vendor-specific memory modules to a specific system. Fujitsu Technology Solutions is known to do this. Adding different memory module to the system usually results in a refusal or other counter-measures (like pressing F1 on every boot).53 43 00 04-EF 4F 8D 1F-00 01 70 00-01 03 C1 CF SC...O....p.....This is the output of a 512 MB memory module from Micron Technologies, branded for Fujitsu-Siemens Computers, note the "FSC" string.The system BIOS rejects memory modules that don't have this information starting at offset 128h.Some Packard Bell AMD laptops also use this method, in this case the symptoms can vary but it can lead to a flashing cursor rather than a beep pattern. Incidentally this can also be a symptom of BIOS corruption as well.WEB,weblink Packard Bell LJ65 RAM upgrade, Tom's Hardware Forum, 9 January 2014, Though upgrading a 2 GB to a 4 GB can also lead to issues.

Reading and writing SPD information

Memory module manufacturers write the SPD information to the EEPROM on the module. Motherboard BIOSes read the SPD information to configure the memory controller. There exist several programs that are able to read and modify SPD information on most, but not all motherboard chipsets.

• dmidecode program that can decode information about memory (and other things) and runs on Linux, FreeBSD, NetBSD, OpenBSD, BeOS, Cygwin and Solaris. dmidecode does not access SPD information directly; it reports the SMBIOS data about the memory.WEB,weblink dmidecode: What's it good for?, 29 November 2004, Linux.com {{pipe, The source for Linux information}} This information may be limited or incorrect.
• On Linux systems and FreeBSD, the user space program decode-dimms provided by i2c-tools decodes and prints information on any memory with SPD information in the computer.WEB, decode-dimms(1), Debian Manpage,weblink 2020-12-16, WEB, decode-dimms,weblink 2021-01-24, www.freebsd.org, It requires SMBus controller support in the kernel, the EEPROM kernel driver, and also that the SPD EEPROMs are connected to the SMBus. On older Linux distributions, decode-dimms.pl was available as part of lm_sensors.
• OpenBSD has included a driver (spdmem(4)) since version 4.3 to provide information about memory modules. The driver was ported from NetBSD, where it is available since release 5.0.
• Coreboot reads and uses SPD information to initialize all memory controllers in a computer with timing, size and other properties.
• Windows systems use programs like HWiNFO,WEB,weblink HWiNFO - Professional System Information and Diagnostics, HWiNFO, CPU-Z and Speccy, which can read and display DRAM module information from SPD.

Chipset-independent reading and writing of SPD information is done by accessing the memory's EEPROM directly with eeprom programmer hardware and software.A not so common use for old laptops is as generic SMBus readers, as the internal EEPROM on the module can be disabled once the BIOS has read it so the bus is essentially available for use. The method used is to pull low the A0,A1 lines so the internal memory shuts down, allowing the external device to access the SMBus. Once this is done, a custom Linux build or DOS application can then access the external device. A common use is recovering data from LCD panel memory chips to retrofit a generic panel into a proprietary laptop.On some chips it is also a good idea to separate write protect lines so that the onboard chips do not get wiped during reprogramming.A related technique is rewriting the chip on webcams often included with many laptops as the bus speed is substantially higher and can even be modified so that 25x compatible chips can be read back for later cloning of the uEFI in the event of a chip failure.This unfortunately only works on DDR3 and below, as DDR4 uses different security and can usually only be read. Its possible to use a tool like SPDTool or similar and replace the chip with one that has its WP line free so it can be altered in situ.On some chipsets the message "Incompatible SMBus driver?" may be seen so read is also prevented.

RGB LED control

Some memory modules (especially on Gaming PCs)WEB, VENGEANCE RGB PRO series DDR4 memory {{!, Desktop Memory {{!}} CORSAIR|url=https://www.corsair.com/us/en/vengeance-rgb-pro-memory|access-date=2020-11-26|website=www.corsair.com}} support RGB LEDs that are controlled by proprietary SMBus commands. This allows LED color control without additional connectors and cables. Kernel drivers from multiple manufacturers required to control the lights have been exploited to gain access ranging from full kernel memory access, to MSR and I/O port control numerous times in 2020 alone.TECH REPORT, Viper RGB Driver Local Privilege Escalation, {{CVE, 2019-18845, |author=ActiveCyber |via=MITRE Corporation |url=https://www.activecyber.us/activelabs/viper-rgb-driver-local-privilege-escalation-cve-2019-18845}}TECH REPORT, CORSAIR iCUE Driver Local Privilege Escalation (CVE-2020-8808), {{CVE, 2020-8808, |author=ActiveCyber |via=MITRE Corporation |url=https://www.activecyber.us/activelabs/corsair-icue-driver-local-privilege-escalation-cve-2020-8808}}TECH REPORT, ACTIVE-2020-003: Trident Z Lighting Control Driver Local Privilege Escalation, {{CVE, 2020-12446, |author=ActiveCyber |via=MITRE Corporation |url=https://www.activecyber.us/activelabs/active-2020-003-trident-z-lighting-control-driver-local-privilege-escalation}}

On older equipment

Some older equipment require the use of SIMMs with parallel presence detect (more commonly called simply presence detect or PD). Some of this equipment uses non-standard PD coding, IBM computers and Hewlett-Packard LaserJet and other printers in particular.

See also

• Transducer electronic data sheet

References

{{Reflist}}

External links

• Serial Presence Detect Standard, General Standard
• SPD Rev1.0 for DDR SDRAM
• SPD Rev1.2 for DDR2 SDRAM
• SPD Rev1.3 for DDR2 SDRAM
• SPECIALITY DDR2-1066 SDRAM
• Linux package i2c-tools
• Instructions on how to use lm-sensors or i2c-tools to read the data {{Webarchive|url=https://web.archive.org/web/20070519080941weblink |date=19 May 2007 }}
• Memory Performance: 16GB DDR3-1333 to DDR3-2400 on Ivy Bridge IGP with G.Skill{{snd}} explanation of various timing values