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{{short description|Quickly accessible working storage available as part of a digital processor}}File:Register.svg|thumb|400px|A register-transfer level (RTL) description of a 8-bit register with detailed implementation, showing how 8 bits of data can be stored.]]A processor register is a quickly accessible location available to a computer’s processor.WEB, What is a processor register?,www.educative.io/answers/what-is-a-processor-register, 2022-08-12, Educative: Interactive Courses for Software Developers, en, Registers usually consist of a small amount of fast storage, although some registers have specific hardware functions, and may be read-only or write-only. In computer architecture, registers are typically addressed by mechanisms other than main memory, but may in some cases be assigned a memory address e.g. DEC PDP-10, ICT 1900.WEB, A Survey of Techniques for Designing and Managing CPU Register File,www.researchgate.net/publication/303802254, Almost all computers, whether load/store architecture or not, load items of data from a larger memory into registers where they are used for arithmetic operations, bitwise operations, and other operations, and are manipulated or tested by machine instructions. Manipulated items are then often stored back to main memory, either by the same instruction or by a subsequent one. Modern processors use either static or dynamic RAM as main memory, with the latter usually accessed via one or more cache levels.Processor registers are normally at the top of the memory hierarchy, and provide the fastest way to access data. The term normally refers only to the group of registers that are directly encoded as part of an instruction, as defined by the instruction set. However, modern high-performance CPUs often have duplicates of these “architectural registers” in order to improve performance via register renaming, allowing parallel and speculative execution. Modern x86 design acquired these techniques around 1995 with the releases of Pentium Pro, Cyrix 6x86, Nx586, and AMD K5.When a computer program accesses the same data repeatedly, this is called locality of reference. Holding frequently used values in registers can be critical to a program’s performance. Register allocation is performed either by a compiler in the code generation phase, or manually by an assembly language programmer.

{{Anchor|RS}}Size

Registers are normally measured by the number of bits they can hold, for example, an “8-bit register”, “32-bit register”, “64-bit register”, or even more. In some instruction sets, the registers can operate in various modes, breaking down their storage memory into smaller parts (32-bit into four 8-bit ones, for instance) to which multiple data (vector, or one-dimensional array of data) can be loaded and operated upon at the same time. Typically it is implemented by adding extra registers that map their memory into a larger register. Processors that have the ability to execute single instructions on multiple data are called vector processors.

Types

A processor often contains several kinds of registers, which can be classified according to the types of values they can store or the instructions that operate on them:

• User-accessible registers can be read or written by machine instructions. The most common division of user-accessible registers is a division into data registers and address registers.
  • {{vanchor|Data register}}s can hold numeric data values such as integers and, in some architectures, floating-point numbers, as well as characters, small bit arrays and other data. In some older architectures, such as the IBM 704, the IBM 709 and successors, the PDP-1, the PDP-4/PDP-7/PDP-9/PDP-15, the PDP-5/PDP-8, and the HP 2100, a special data register known as the accumulator is used implicitly for many operations.
  • {{vanchor|Address register}}s hold addresses and are used by instructions that indirectly access primary memory.
    • Some processors contain registers that may only be used to hold an address or only to hold numeric values (in some cases used as an index register whose value is added as an offset from some address); others allow registers to hold either kind of quantity. A wide variety of possible addressing modes, used to specify the effective address of an operand, exist.
    • The stack pointer is used to manage the run-time stack. Rarely, other data stacks are addressed by dedicated address registers (see stack machine).
  • General-purpose registers ({{Vanchor|GPR}}s) can store both data and addresses, i.e., they are combined data/address registers; in some architectures, the register file is unified so that the GPRs can store floating-point numbers as well.
  • Status registers hold truth values often used to determine whether some instruction should or should not be executed.
  • {{vanchor|Floating-point register|FLOATING_POINT_REGISTER|floating point register}}s (FPRs) store floating-point numbers in many architectures.
  • Constant registers hold read-only values such as zero, one, or pi.
  • {{visible anchor|Vector registers}} hold data for vector processing done by SIMD instructions (Single Instruction, Multiple Data).
  • Special-purpose registers (SPRs) hold some elements of the program state; they usually include the program counter, also called the instruction pointer, and the status register; the program counter and status register might be combined in a program status word (PSW) register. The aforementioned stack pointer is sometimes also included in this group. Embedded microprocessors can also have registers corresponding to specialized hardware elements.
  • In some architectures, model-specific registers (also called machine-specific registers) store data and settings related to the processor itself. Because their meanings are attached to the design of a specific processor, they cannot be expected to remain standard between processor generations.
  • Memory type range registers (MTRRs)
• {{Vanchor|Internal register}}s are not accessible by instructions and are used internally for processor operations.
  • The instruction register holds the instruction currently being executed.
  • Registers related to fetching information from RAM, a collection of storage registers located on separate chips from the CPU:
    • Memory buffer register (MBR), also known as memory data register (MDR)
    • Memory address register (MAR)
• Architectural registers{{anchor|ARCHITECTURAL}} are the registers visible to software and are defined by an architecture. They may not correspond to the physical hardware if register renaming is being performed by the underlying hardware.

Hardware registers are similar, but occur outside CPUs.In some architectures (such as SPARC and MIPS), the first or last register in the integer register file is a pseudo-register in that it is hardwired to always return zero when read (mostly to simplify indexing modes), and it cannot be overwritten. In Alpha, this is also done for the floating-point register file. As a result of this, register files are commonly quoted as having one register more than how many of them are actually usable; for example, 32 registers are quoted when only 31 of them fit within the above definition of a register.

Examples

The following table shows the number of registers in several mainstream CPU architectures. Note that in x86-compatible processors, the stack pointer (ESP) is counted as an integer register, even though there are a limited number of instructions that may be used to operate on its contents. Similar caveats apply to most architectures.Although all of the below-listed architectures are different, almost all are in a basic arrangement known as the von Neumann architecture, first proposed by the Hungarian-American mathematician John von Neumann. It is also noteworthy that the number of registers on GPUs is much higher than that on CPUs.{| class=“wikitable sortable” align=“left“! Architecture ! {{nowrap|GPRs/data+address registers}}! {{nowrap|FP registers}}! Notes

AT&T Hobbit >	stack of 7	All data manipulation instructions work solely within registers, and data must be moved into a register before processing.

Cray-1HTTP://WWW.BITSAVERS.ORG/PDF/CRAY/CRAY-1/2240004C_CRAY-1_HARDWARE_REFERENCE_NOV77.PDF	PUBLISHER=CRAY RESEARCH	ACCESS-DATE=2022-12-23	ARCHIVE-URL=HTTPS://WEB.ARCHIVE.ORG/WEB/20211107213641/HTTP://WWW.BITSAVERS.ORG/PDF/CRAY/CRAY-1/2240004C_CRAY-1_HARDWARE_REFERENCE_NOV77.PDF

4004HTTP://BITSAVERS.ORG/PDF/INTEL/MCS4/MCS-4_USERSMANUAL_FEB73.PDF	PUBLISHER=INTEL			00}}0

8008HTTP://BITSAVERS.ORG/PDF/INTEL/MCS8/8008USERSMANUALREV4_NOV73.PDF	PUBLISHER=INTEL	ACCESS-DATE=JANUARY 23, 2014,	style="text-align:center;”		floating-point unit (FPU) available.

8080HTTP://BITSAVERS.ORG/PDF/INTEL/MCS80/98-153B_INTEL_8080_MICROCOMPUTER_SYSTEMS_USERS_MANUAL_197509.PDF	PUBLISHER=INTEL	ACCESS-DATE=JANUARY 23, 2014,	style="text-align:center;”		Intel 8231, AMD Am9511, and Intel 8232. They were also readily usable with the Z80 and similar processors.

iAPX432 >	stack of 6	Stack machine

X86#16-bit>16-bit x86HTTP://WWW.BITSAVERS.ORG/PDF/INTEL/80286/210498-005_80286_AND_80287_PROGRAMMERS_REFERENCE_MANUAL_1987.PDF>TITLE=80286 AND 80287 PROGRAMMER’S REFERENCE MANUAL	YEAR=1987,	style="text-align:center;”	00}}6	style="text-align:center;” | stack of 8(if FP present)	Intel 8086>8086/Intel 8088	, Intel 80186>80186/Intel 80188	, and Intel 80286>80286 processors, if provided an Intel 8087	, Intel 80187>80187 or 80287 co-processor for floating-point operations, support an 80-bit wide, 8 deep register stack with some instructions able to use registers relative to the top of the stack as operands; without a co-processor, no floating-point registers are supported.

IA-32HTTP://WWW.INTEL.COM/CONTENT/WWW/US/EN/PROCESSORS/ARCHITECTURES-SOFTWARE-DEVELOPER-MANUALS.HTML	DATE=4 DECEMBER 2019		stack of 8 (if FP present),8 (if SSE/MMX present)	Intel 80386>80386 processor requires an Intel 80387	for floating-point operations, later processors had built-in floating-point, with both having an 80-bit wide, 8 deep register stack with some instructions able to use registers relative to the top of the stack as operands. The Pentium III and later had the Streaming SIMD Extensions>SSE with additional 128-bit XMM registers.

x86-64HTTP://SUPPORT.AMD.COM/TECHDOCS/24592.PDF	PUBLISHER=AMD		16 or 32(if AVX-512 available)	Advanced Vector Extensions>AVX/AVX2 and 512-bit ZMM0–ZMM31 registers with AVX-512.HTTPS://SOFTWARE.INTEL.COM/SITES/DEFAULT/FILES/MANAGED/C5/15/ARCHITECTURE-INSTRUCTION-SET-EXTENSIONS-PROGRAMMING-REFERENCE.PDF>TITLE=INTEL ARCHITECTURE INSTRUCTION SET EXTENSIONS AND FUTURE FEATURES PROGRAMMING REFERENCE	INTEL>DATE=JANUARY 2018,

Fairchild F8 >
Geode GX >		00}}8	Geode GX/Media GX/4x86/cx5x86	is the emulation of 486/Pentium compatible processor made by Cyrix/National Semiconductor. Like Transmeta, the processor had a translation layer that translated x86 code to native code and executed it.{{citation needed>date=February 2016}} It does not support 128-bit SSE registers, just the 80387 stack of eight 80-bit floating-point registers, and partially supports 3DNow! from AMD. The native processor only contains 1 data and 1 address register for all purposes and it is translated into 4 paths of 32-bit naming registers r1 (base), r2 (data), r3 (back pointer), and r4 (stack pointer) within scratchpad SRAM for integer operations.{{cn|date=May 2023}}

V.Smile>SunPlus SPG	style="text-align:center;”	00}}0	style="text-align:center;”	6 stack + 4 SIMD}}	A 16-bit wide, 32-bit address space stack machine processor from the Taiwanese company Sunplus Technology, it can be found on Vtech’s V.Smile line for educational purposes and video game consoles such as the Wireless 60, Mattel HyperScan, and XaviXPORT. It lacks any general-purpose register or internal register for naming/renaming, but its floating-point unit has an 80-bit 6-stage stack and four 128-bit VLIW SIMD registers on a vertex shader co-processor.

Nuon (DVD technology)>VM Labs Nuon	style="text-align:center;”	00}}0	style="text-align:center;”	00}}1	A 32-bit stack machine processor developed by VM Labs and specialized for multimedia. It can be found on the company’s own Nuon DVD player console line and the Game Wave Family Entertainment System from ZaPit games. The design was heavily influenced by Intel’s MMX technology; it contained a 128-byte unified stack cache for both vector and scalar instructions. The unified cache can be divided as eight 128-bit vector registers or thirty-two 32-bit SIMD scalar registers through bank renaming; there is no integer register in this architecture.

Nios IIHTTPS://WWW.ALTERA.COM/EN_US/PDFS/LITERATURE/HB/NIOS2/N2CPU_NII5V1.PDF	PUBLISHER=ALTERA		PUBLISHER=ALTERA		{{0		date=February 2016}} and has 31 32-bit GPRs, with register 0 being hardwired to zero, and eight 64-bit floating-point registers{{citation needed|date=February 2016}}

Motorola 6800HTTP://BITSAVERS.ORG/PDF/MOTOROLA/6800/MOTOROLA_M6800_PROGRAMMING_REFERENCE_MANUAL_M68PRM(D)_NOV76.PDF	PUBLISHER=MOTOROLA	ACCESS-DATE=MAY 18, 2015,	style="text-align:center;”
Motorola 68kHTTP://WWW.FREESCALE.COM/FILES/ARCHIVES/DOC/REF_MANUAL/M68000PRM.PDF	PUBLISHER=MOTOROLA	ACCESS-DATE=JUNE 13, 2015,	style="text-align:center;”
SuperH>SH 16-bit	style="text-align:center;”	00}}16	style="text-align:center;”	00}}6

Emotion Engine >

CUDA}}CUDAHTTPS://DOCS.NVIDIA.COM/CUDA/CUDA-C-PROGRAMMING-GUIDE/INDEX.HTML#COMPUTE-CAPABILITIES>TITLE=CUDA C PROGRAMMING GUIDE	YEAR=2019		Tesla_(microarchitecture)	/Fermi_(microarchitecture)>Fermi). The more registers are configured per thread, the fewer threads can run at the same time. Registers are 32 bits wide; double-precision floating-point numbers and 64-bit pointers therefore require two registers. It additionally has up to 8 predicate registers per thread.DISSECTING THE NVIDIA VOLTA GPU ARCHITECTURE VIA MICROBENCHMARKING >YEAR=2018	LAST1=JIA	LAST2=MAGGIONI	LAST3=STAIGER	LAST4=SCARPAZZA	CLASS=CS.DC,

CDC 6000 series >	{{0	| 8 ‘A’ registers, A0–A7, hold 18-bit addresses; 8 ‘B’ registers, B0–B7, hold 18-bit integer values (with B0 permanently set to zero); 8 ‘X’ registers, X0–X7, hold 60 bits of integer or floating-point data. Seven of the eight 18-bit A registers were coupled to their corresponding X registers: setting any of the A1–A5 registers to a value caused a memory load of the contents of that address into the corresponding X register. Likewise, setting an address into registers A6 or A7 caused a memory store into that location in memory from X6 or X7. (Registers A0 and X0 were not coupled like this).

System/360, System/370, System/390, z/Architecture >	4 (if FP present);16 in G5 and later S/390 models and z/Architecture		PUBLISHER=IBM	ACCESS-DATE=MAY 11, 2020, Some registers are assigned a fixed purpose by calling conventions; for example, register 14 is used for subroutine return addresses and, for Executable and Linkable Format	ABIs, register 15 is used as a stack pointer. The S/390 G5 processor increased the number of floating-point registers to 16.HTTPS://OLD.HOTCHIPS.ORG/WP-CONTENT/UPLOADS/HC_ARCHIVES/HC10/2_MON/HC10.S5/HC10.5.1.PDF, IBM S/390 G5 Microprocessor,

MMIXHTTP://MMIX.CS.HM.EDU			| An instruction set designed by Donald Knuth in the late 1990s for pedagogical purposes.

NS320xxHTTP://BITSAVERS.ORG/COMPONENTS/NATIONAL/_DATABOOKS/1986_NATIONAL_NS32000_DATABOOK.PDF	PUBLISHER=NATIONAL SEMICONDUCTOR,	style="text-align:center;”	00}}8	style="text-align:center;”	00}}8(if FP present)|

Xelerated X10 >	{{0		date=March 2019}}

Parallax Propeller >	{{0	| An eight-core 8/16-bit sliced stack machine controller with a simple logic circuit inside, it has 8 cog counters (cores), each containing three 8/16 bit special control registers with 32 bit x 512 stack RAM. However, it does not contain any general register for integer purposes. Unlike most shadow register files in modern processors and multi-core systems, all of the stack RAM in cog can be accessed in instruction level, which allows all of these cogs to act as a single general-purpose core if necessary. Floating-point unit is external and it contains two 80-bit vector registers.

Itanium >		| And 64 1-bit predicate registers and 8 branch registers. The FP registers are 82-bit.

SPARC >	{{0	| Global register 0 is hardwired to 0. Uses register windows.

IBM POWER Instruction Set Architecture>IBM POWER	style="text-align:center;”	0}}32	style="text-align:center;”	0}}32	Also included are a link register, a count register, and a multiply quotient (MQ) register.

PowerPC/Power ISA >	{{0		AltiVec>Vector facility also have 32 128-bit vector registers.

Blackfin >		00}}0	Also included are a stack pointer and a frame pointer. Additional registers are used to implement zero-overhead loops and circular buffer DAGs (data address generators).

IBM Cell#Synergistic Processing Elements (SPE)>IBM Cell SPE	style="text-align: center” colspan=“2”			PUBLISHER=IBM, January 27, 2007,

DEC PDP-10>PDP-10	style="text-align: center” colspan=“2”	0}}16	All of the registers may be used generally (integer, float, stack pointer, jump, indexing, etc.). Every 36-bit memory (or register) word can also be manipulated as a half-word, which can be considered an (18-bit) address. Other word interpretations are used by certain instructions. In the original PDP-10 processors, these 16 GPRs also corresponded to main (i.e. Magnetic-core memory	) memory locations 0–15; a hardware option called “fast memory” implemented the registers as separate ICs, and references to memory locations 0–15 referred to the IC registers. Later models implemented the registers as “fast memory” and continued to make memory locations 0–15 refer to them. Movement instructions take (register, memory) operands: {{code>MOVE 1,2}} is register-register, and {{code|MOVE 1,1000}} is memory-to-register.

DEC PDP-11>PDP-11	style="text-align:center;”	00}}7	style="text-align:center;”	00}}6(if FPP present)| R7 is the program counter. Any register can be a stack pointer but R6 is used for hardware interrupts and traps.

DEC VAX>VAX	style="text-align: center” colspan=“2”	0}}16	The general purpose registers are used for floating-point values as well. Three of the registers have special uses: R12 (Argument Pointer), R13 (Frame Pointer), and R14 (Stack Pointer), while R15 refers to the Program Counter.

DEC Alpha>Alpha	style="text-align:center;”	0}}31	style="text-align:center;”	0}}31	Registers R31 (integer) and F31 (floating-point) are hardwired to zero.

MOS Technology 6502>6502	style="text-align:center;”
65C816>W65C816S	style="text-align:center;”	00}}1	style="text-align:center;”	00}}0	65c816 is the 16-bit successor of the 6502. X, Y, and D (Direct Page register) are condition registers and SP register are specific index only. Main accumulator extended to 16-bit (C)HTTPS://WIKI.SUPERFAMICOM.ORG/LEARNING-65816-ASSEMBLY#TOC-2>TITLE=LEARNING 65816 ASSEMBLY	ACCESS-DATE=14 NOVEMBER 2019, while keeping 8-bit (A) for compatibility and main registers can now address up to 24-bit (16-bit wide data instruction/24-bit memory address).

Media-embedded processor>MeP	style="text-align:center;”	00}}4	style="text-align:center;”	00}}8	Media-embedded processor was a 32-bit processor developed by Toshiba with a modded 8080 instruction set. Only the A, B, C, and D registers are available through all modes (8/16/32-bit). It is incompatible with x86; however, it contains an 80-bit floating-point unit that is x87-compatible.

PIC microcontroller >	{{0	|

Atmel AVR>AVR microcontroller	style="text-align:center;”	0}}32	style="text-align:center;”	00}}0

ARM architecture>ARM 32-bit (ARM/A32, Thumb-2/T32)	style="text-align:center;”	0}}14	style="text-align:center;” | Varies(up to 32)		PUBLISHER=ARM HOLDINGS	ACCESS-DATE=27 MAY 2013, and used upper bits of the program counter (r15) for status flags, making that register 32-bit.

ARM architecture>ARM 32-bit (Thumb)	style="text-align:center;”	00}}8	style="text-align:center;”	0}}16	Version 1 of Thumb, which only supported access to registers r0 through r7HTTPS://DEVELOPER.ARM.COM/DOCS/DDI0210/LATEST/PROGRAMMERS-MODEL/REGISTERS/THE-THUMB-STATE-REGISTER-SET>TITLE=2.6.2. THE THUMB-STATE REGISTER SET	PUBLISHER=ARM HOLDINGS,

ARM architecture>ARM 64-bit (A64)HTTP://INFOCENTER.ARM.COM/HELP/TOPIC/COM.ARM.DOC.IHI0055A/IHI0055A_AAPCS64.PDF>TITLE=PROCEDURE CALL STANDARD FOR THE ARM 64-BIT ARCHITECTURE	DATE=22 MAY 2013		{{0	| Register r31 is the stack pointer or hardwired to 0, depending on the context.

MIPS architecture>MIPS	style="text-align:center;”	0}}31	style="text-align:center;”	0}}32	Integer register 0 is hardwired to 0.

RISC-V >	{{0	| Integer register 0 is hardwired to 0. The RV32E variant, intended for systems with very limited resources, has 15 integer registers.

Adapteva>Epiphany	style="text-align: center” colspan=“2”		| Each instruction controls whether registers are interpreted as integers or single precision floating point. Architecture is scalable to 4096 cores with 16 and 64 core implementations currently available.

{{Clear}}

Usage

The number of registers available on a processor and the operations that can be performed using those registers has a significant impact on the efficiency of code generated by optimizing compilers. The Strahler number of an expression tree gives the minimum number of registers required to evaluate that expression tree.

See also

• CPU cache
• Quantum register
• Register allocation
• Register file
• Shift register

References

{{Reflist|30em}}{{CPU technologies}}{{X86 assembly topics}}{{Authority control}}