random-access memory

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random-access memory
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{{Redirect|RAM|other uses|Ram (disambiguation){{!}}Ram}}{{pp-protected|small=yes}}{{short description|Form of computer data storage}}{{Memory types}}File:Swissbit 2GB PC2-5300U-555.jpg|right|thumb|Example of writable volatile random-access memory: Synchronous Dynamic RAM modules, primarily used as main memory in personal computers, workstations, and servers.]]Random-access memory (RAM {{IPAc-en|r|æ|m}}) is a form of computer memory that can be read and changed in any order, typically used to store working data and machine code.WEB, RAM,weblink Cambridge English Dictionary, 11 July 2019, WEB, RAM,weblink Oxford Advanced Learner's Dictionary, 11 July 2019, A random-access memory device allows data items to be read or written in almost the same amount of time irrespective of the physical location of data inside the memory. In contrast, with other direct-access data storage media such as hard disks, CD-RWs, DVD-RWs and the older magnetic tapes and drum memory, the time required to read and write data items varies significantly depending on their physical locations on the recording medium, due to mechanical limitations such as media rotation speeds and arm movement.RAM contains multiplexing and demultiplexing circuitry, to connect the data lines to the addressed storage for reading or writing the entry. Usually more than one bit of storage is accessed by the same address, and RAM devices often have multiple data lines and are said to be "8-bit" or "16-bit", etc. devices.In today's technology, random-access memory takes the form of integrated circuit (IC) chips with MOS (metal-oxide-semiconductor) memory cells. RAM is normally associated with volatile types of memory (such as DRAM modules), where stored information is lost if power is removed, although non-volatile RAM has also been developed.WEB, Gallagher, Sean, Memory that never forgets: non-volatile DIMMs hit the market,weblink Ars Technica, no,weblink 2017-07-08, 2013-04-04, Other types of non-volatile memories exist that allow random access for read operations, but either do not allow write operations or have other kinds of limitations on them. These include most types of ROM and a type of flash memory called NOR-Flash.The two main types of volatile random-access semiconductor memory are static random-access memory (SRAM) and dynamic random-access memory (DRAM). Commercial uses of semiconductor RAM date back to 1965, when IBM introduced the SP95 SRAM chip for their System/360 Model 95 computer, and Toshiba used DRAM memory cells for its Toscal BC-1411 electronic calculator, both based on bipolar transistors. Commercial MOS memory, based on MOS transistors, was developed in the late 1960s, and has since been the basis for all commercial semiconductor memory. The first commercial DRAM IC chip, the Intel 1103, was introduced in October 1970. Synchronous dynamic random-access memory (SDRAM) later debuted with the Samsung KM48SL2000 chip in 1992.


File:Early SSA accounting operations.jpg|thumb|These IBM tabulating machines from the 1930s used mechanical countermechanical counterFile:8 bytes vs. 8Gbytes.jpg|thumb|A portion of a core memory with a modern flash SD cardSD cardFile:Bundesarchiv Bild 183-1989-0406-022, VEB Carl Zeiss Jena, 1-Megabit-Chip.jpg|thumb|left|1 Megabit chip – one of the last models developed by VEB Carl Zeiss Jena in 1989]]Early computers used relays, mechanical countersWEB,weblink IBM Archives -- FAQ's for Products and Services,, no,weblink" title="">weblink 2012-10-23, or delay lines for main memory functions. Ultrasonic delay lines could only reproduce data in the order it was written. Drum memory could be expanded at relatively low cost but efficient retrieval of memory items required knowledge of the physical layout of the drum to optimize speed. Latches built out of vacuum tube triodes, and later, out of discrete transistors, were used for smaller and faster memories such as registers. Such registers were relatively large and too costly to use for large amounts of data; generally only a few dozen or few hundred bits of such memory could be provided.The first practical form of random-access memory was the Williams tube starting in 1947. It stored data as electrically charged spots on the face of a cathode ray tube. Since the electron beam of the CRT could read and write the spots on the tube in any order, memory was random access. The capacity of the Williams tube was a few hundred to around a thousand bits, but it was much smaller, faster, and more power-efficient than using individual vacuum tube latches. Developed at the University of Manchester in England, the Williams tube provided the medium on which the first electronically stored program was implemented in the Manchester Baby computer, which first successfully ran a program on 21 June 1948.{{Citation | last = Napper | first = Brian | title = Computer 50: The University of Manchester Celebrates the Birth of the Modern Computer | url =weblink | accessdate = 26 May 2012 | deadurl = yes | archiveurl =weblink" title="">weblink | archivedate = 4 May 2012 | df = }} In fact, rather than the Williams tube memory being designed for the Baby, the Baby was a testbed to demonstrate the reliability of the memory.{{Citation|last1=Williams|first1=F.C.|last2=Kilburn|first2=T.|title=Electronic Digital Computers|journal=Nature|volume=162|pages=487|date=Sep 1948|doi=10.1038/162487a0|issue=4117|postscript=.}} Reprinted in The Origins of Digital Computers{{Citation|last1=Williams|first1=F.C.|last2=Kilburn|first2=T.|last3=Tootill|first3=G.C.|title=Universal High-Speed Digital Computers: A Small-Scale Experimental Machine|url=|journal=Proc. IEE|date=Feb 1951|volume=98|issue=61|pages=13–28|postscript=.|doi=10.1049/pi-2.1951.0004|deadurl=yes|archiveurl=|archivedate=2013-11-17|df=}}Magnetic-core memory was invented in 1947 and developed up until the mid-1970s. It became a widespread form of random-access memory, relying on an array of magnetized rings. By changing the sense of each ring's magnetization, data could be stored with one bit stored per ring. Since every ring had a combination of address wires to select and read or write it, access to any memory location in any sequence was possible. Magnetic core memory was the standard form of computer memory system until displaced by solid-state MOS (metal-oxide-silicon) semiconductor memory in integrated circuits (ICs) during the early 1970s.Prior to the development of integrated read-only memory (ROM) circuits, permanent (or read-only) random-access memory was often constructed using diode matrices driven by address decoders, or specially wound core rope memory planes. {{Citation needed|reason=This paragraph needs a citation.|date=December 2016}}

Semiconductor RAM

Semiconductor memory began in the 1960s with bipolar memory, which used bipolar transistors. While it improved performance, it could not compete with the lower price of magnetic core memory.WEB, 1966: Semiconductor RAMs Serve High-speed Storage Needs,weblink Computer History Museum, 19 June 2019, The invention of the MOSFET (metal-oxide-semiconductor field-effect transistor), also known as the MOS transistor, by Mohamed Atalla and Dawon Kahng at Bell Labs in 1959,JOURNAL,weblink 1960 - Metal Oxide Semiconductor (MOS) Transistor Demonstrated, The Silicon Engine, Computer History Museum, led to the development of MOS semiconductor memory by John Schmidt at Fairchild Semiconductor in 1964.BOOK,weblink Solid State Design - Vol. 6, 1965, Horizon House, In addition to higher performance, MOS memory was cheaper and consumed less power than magnetic core memory.WEB, 1970: Semiconductors compete with magnetic cores,weblink Computer History Museum, 19 June 2019, The development of silicon-gate MOS integrated circuit (IC) technology by Federico Faggin at Fairchild in 1968 enabled the production of MOS memory chips.WEB, 1968: Silicon Gate Technology Developed for ICs,weblink Computer History Museum, 10 August 2019, MOS memory overtook magnetic core memory as the dominant memory technology in the early 1970s.An integrated bipolar static random-access memory (SRAM) was invented by Robert H. Norman at Fairchild Semiconductor in 1963.PATENT, US, 3562721, patent, Solid State Switching and Memory Apparatus, 9 February1971, 5 March 1963, 5 March 1963, Robert H. Norman, Fairchild Camera and Instrument Corporation, It was followed by the development of MOS SRAM by John Schmidt at Fairchild in 1964. Commercial use of SRAM began in 1965, when IBM introduced the SP95 memory chip for the System/360 Model 95.Dynamic random-access memory (DRAM) allowed replacement of a 4 or 6-transistor latch circuit by a single transistor for each memory bit, greatly increasing memory density at the cost of volatility. Data was stored in the tiny capacitance of each transistor, and had to be periodically refreshed every few milliseconds before the charge could leak away. Toshiba's Toscal BC-1411 electronic calculator, which was introduced in 1965,Toscal BC-1411 calculator {{webarchive|url= |date=2017-07-29 }}, Science Museum, London used a form of capacitive bipolar DRAM, storing 180-bit data on discrete memory cells, consisting of germanium bipolar transistors and capacitors. In 1967, Robert H. Dennard of IBM filed a patent for a single-transistor MOS DRAM memory cell, using a MOSFET transistor.WEB, Robert Dennard,weblink Encyclopedia Britannica, 8 July 2019, The first commercial DRAM IC chip was the Intel 1103, which was manufactured on an 8{{nbsp}}µm MOS process with a capacity of 1{{nbsp}}kb, and was released in 1970.WEB, Mary, Bellis,weblink The Invention of the Intel 1103, Synchronous dynamic random-access memory (SDRAM) was developed by Samsung Electronics. The first commercial SDRAM chip was the Samsung KM48SL2000, which had a capacity of 16{{nbsp}}Mb.JOURNAL, Electronic Design, Electronic Design, 1993, 41, 15–21,weblink Hayden Publishing Company, The first commercial synchronous DRAM, the Samsung 16-Mbit KM48SL2000, employs a single-bank architecture that lets system designers easily transition from asynchronous to synchronous systems., It was introduced by Samsung in 1992,WEB, KM48SL2000-7 Datasheet,weblink Samsung, 19 June 2019, August 1992, and mass-produced in 1993. The first commercial DDR SDRAM (double data rate SDRAM) memory chip was Samsung's 64{{nbsp}}Mb DDR SDRAM chip, released in June 1998.NEWS, Samsung Electronics Develops First 128Mb SDRAM with DDR/SDR Manufacturing Option,weblink 23 June 2019, Samsung Electronics, Samsung, 10 February 1999, GDDR (graphics DDR) is a form of DDR SGRAM (synchronous graphics RAM), which was first released by Samsung as a 16{{nbsp}}Mb memory chip in 1998.NEWS, Samsung Electronics Comes Out with Super-Fast 16M DDR SGRAMs,weblink 23 June 2019, Samsung Electronics, Samsung, 17 September 1998,


The two widely used forms of modern RAM are static RAM (SRAM) and dynamic RAM (DRAM). In SRAM, a bit of data is stored using the state of a six-transistor memory cell. This form of RAM is more expensive to produce, but is generally faster and requires less dynamic power than DRAM. In modern computers, SRAM is often used as cache memory for the CPU. DRAM stores a bit of data using a transistor and capacitor pair, which together comprise a DRAM cell. The capacitor holds a high or low charge (1 or 0, respectively), and the transistor acts as a switch that lets the control circuitry on the chip read the capacitor's state of charge or change it. As this form of memory is less expensive to produce than static RAM, it is the predominant form of computer memory used in modern computers.Both static and dynamic RAM are considered volatile, as their state is lost or reset when power is removed from the system. By contrast, read-only memory (ROM) stores data by permanently enabling or disabling selected transistors, such that the memory cannot be altered. Writeable variants of ROM (such as EEPROM and flash memory) share properties of both ROM and RAM, enabling data to persist without power and to be updated without requiring special equipment. These persistent forms of semiconductor ROM include USB flash drives, memory cards for cameras and portable devices, and solid-state drives. ECC memory (which can be either SRAM or DRAM) includes special circuitry to detect and/or correct random faults (memory errors) in the stored data, using parity bits or error correction codes.In general, the term RAM refers solely to solid-state memory devices (either DRAM or SRAM), and more specifically the main memory in most computers. In optical storage, the term DVD-RAM is somewhat of a misnomer since, unlike CD-RW or DVD-RW it does not need to be erased before reuse. Nevertheless, a DVD-RAM behaves much like a hard disc drive if somewhat slower.

Memory cell

The memory cell is the fundamental building block of computer memory. The memory cell is an electronic circuit that stores one bit of binary information and it must be set to store a logic 1 (high voltage level) and reset to store a logic 0 (low voltage level). Its value is maintained/stored until it is changed by the set/reset process. The value in the memory cell can be accessed by reading it.In SRAM, the memory cell is a type of flip-flop circuit, usually implemented using FETs. This means that SRAM requires very low power when not being accessed, but it is expensive and has low storage density.A second type, DRAM, is based around a capacitor. Charging and discharging this capacitor can store a "1" or a "0" in the cell. However, the charge in this capacitor slowly leaks away, and must be refreshed periodically. Because of this refresh process, DRAM uses more power, but it can achieve greater storage densities and lower unit costs compared to SRAM.{| style="text-align:center; margin: 1em auto 1em auto"
thumbthumb|DRAM Cell (1 Transistor and one capacitor))


To be useful, memory cells must be readable and writeable. Within the RAM device, multiplexing and demultiplexing circuitry is used to select memory cells. Typically, a RAM device has a set of address lines A0... An, and for each combination of bits that may be applied to these lines, a set of memory cells are activated. Due to this addressing, RAM devices virtually always have a memory capacity that is a power of two.Usually several memory cells share the same address. For example, a 4 bit 'wide' RAM chip has 4 memory cells for each address. Often the width of the memory and that of the microprocessor are different, for a 32 bit microprocessor, eight 4 bit RAM chips would be needed.Often more addresses are needed than can be provided by a device. In that case, external multiplexors to the device are used to activate the correct device that is being accessed.

Memory hierarchy

One can read and over-write data in RAM. Many computer systems have a memory hierarchy consisting of processor registers, on-die SRAM caches, external caches, DRAM, paging systems and virtual memory or swap space on a hard drive. This entire pool of memory may be referred to as "RAM" by many developers, even though the various subsystems can have very different access times, violating the original concept behind the random access term in RAM. Even within a hierarchy level such as DRAM, the specific row, column, bank, rank, channel, or interleave organization of the components make the access time variable, although not to the extent that access time to rotating storage media or a tape is variable. The overall goal of using a memory hierarchy is to obtain the highest possible average access performance while minimizing the total cost of the entire memory system (generally, the memory hierarchy follows the access time with the fast CPU registers at the top and the slow hard drive at the bottom).In many modern personal computers, the RAM comes in an easily upgraded form of modules called memory modules or DRAM modules about the size of a few sticks of chewing gum. These can quickly be replaced should they become damaged or when changing needs demand more storage capacity. As suggested above, smaller amounts of RAM (mostly SRAM) are also integrated in the CPU and other ICs on the motherboard, as well as in hard-drives, CD-ROMs, and several other parts of the computer system.

Other uses of RAM

File:Samsung-1GB-DDR2-Laptop-RAM.jpg|thumb|right|A SO-DIMM stick of laptop RAM, roughly half the size of desktop RAM.]]In addition to serving as temporary storage and working space for the operating system and applications, RAM is used in numerous other ways.

Virtual memory

Most modern operating systems employ a method of extending RAM capacity, known as "virtual memory". A portion of the computer's hard drive is set aside for a paging file or a scratch partition, and the combination of physical RAM and the paging file form the system's total memory. (For example, if a computer has 2 GB of RAM and a 1 GB page file, the operating system has 3 GB total memory available to it.) When the system runs low on physical memory, it can "swap" portions of RAM to the paging file to make room for new data, as well as to read previously swapped information back into RAM. Excessive use of this mechanism results in thrashing and generally hampers overall system performance, mainly because hard drives are far slower than RAM.

RAM disk

Software can "partition" a portion of a computer's RAM, allowing it to act as a much faster hard drive that is called a RAM disk. A RAM disk loses the stored data when the computer is shut down, unless memory is arranged to have a standby battery source.

Shadow RAM

Sometimes, the contents of a relatively slow ROM chip are copied to read/write memory to allow for shorter access times. The ROM chip is then disabled while the initialized memory locations are switched in on the same block of addresses (often write-protected). This process, sometimes called shadowing, is fairly common in both computers and embedded systems.As a common example, the BIOS in typical personal computers often has an option called “use shadow BIOS” or similar. When enabled, functions that rely on data from the BIOS's ROM instead use DRAM locations (most can also toggle shadowing of video card ROM or other ROM sections). Depending on the system, this may not result in increased performance, and may cause incompatibilities. For example, some hardware may be inaccessible to the operating system if shadow RAM is used. On some systems the benefit may be hypothetical because the BIOS is not used after booting in favor of direct hardware access. Free memory is reduced by the size of the shadowed ROMs.WEB,weblink Shadow Ram, 2007-07-24, no,weblink" title="">weblink 2006-10-29, '''

Recent developments

Several new types of non-volatile RAM, which preserve data while powered down, are under development. The technologies used include carbon nanotubes and approaches utilizing Tunnel magnetoresistance. Amongst the 1st generation MRAM, a 128 KiB ({{nowrap|128 × 210}} bytes) chip was manufactured with 0.18 Âµm technology in the summer of 2003.{{citation needed|date=June 2015}} In June 2004, Infineon Technologies unveiled a 16 MiB (16 Ã— 220 bytes) prototype again based on 0.18 Âµm technology. There are two 2nd generation techniques currently in development: thermal-assisted switching (TAS)The Emergence of Practical MRAM WEB,weblink Crocus Technology | Magnetic Sensors | TMR Sensors, 2009-07-20, yes,weblink" title="">weblink 2011-04-27, which is being developed by Crocus Technology, and spin-transfer torque (STT) on which Crocus, Hynix, IBM, and several other companies are working.WEB,weblink Tower invests in Crocus, tips MRAM foundry deal, EETimes, no,weblink" title="">weblink 2012-01-19, Nantero built a functioning carbon nanotube memory prototype 10 GiB (10 Ã— 230 bytes) array in 2004. Whether some of these technologies can eventually take significant market share from either DRAM, SRAM, or flash-memory technology, however, remains to be seen.Since 2006, "solid-state drives" (based on flash memory) with capacities exceeding 256 gigabytes and performance far exceeding traditional disks have become available. This development has started to blur the definition between traditional random-access memory and "disks", dramatically reducing the difference in performance.Some kinds of random-access memory, such as "EcoRAM", are specifically designed for server farms, where low power consumption is more important than speed."EcoRAM held up as less power-hungry option than DRAM for server farms" {{webarchive|url= |date=2008-06-30 }}by Heather Clancy 2008

Memory wall

The "memory wall" is the growing disparity of speed between CPU and memory outside the CPU chip. An important reason for this disparity is the limited communication bandwidth beyond chip boundaries, which is also referred to as bandwidth wall. From 1986 to 2000, CPU speed improved at an annual rate of 55% while memory speed only improved at 10%. Given these trends, it was expected that memory latency would become an overwhelming bottleneck in computer performance.The term was coined in WEB,weblink Archived copy, 2011-12-14, no,weblink" title="">weblink 2012-04-06, .CPU speed improvements slowed significantly partly due to major physical barriers and partly because current CPU designs have already hit the memory wall in some sense. Intel summarized these causes in a 2005 document.WEB, Platform 2015: Intel® Processor and Platform Evolution for the Next Decade, March 2, 2005,weblink no,weblink" title="">weblink April 27, 2011, First of all, as chip geometries shrink and clock frequencies rise, the transistor leakage current increases, leading to excess power consumption and heat... Secondly, the advantages of higher clock speeds are in part negated by memory latency, since memory access times have not been able to keep pace with increasing clock frequencies. Third, for certain applications, traditional serial architectures are becoming less efficient as processors get faster (due to the so-called Von Neumann bottleneck), further undercutting any gains that frequency increases might otherwise buy. In addition, partly due to limitations in the means of producing inductance within solid state devices, resistance-capacitance (RC) delays in signal transmission are growing as feature sizes shrink, imposing an additional bottleneck that frequency increases don't address.The RC delays in signal transmission were also noted in "Clock Rate versus IPC: The End of the Road for Conventional Microarchitectures"CONFERENCE, Vikas, Agarwal, M. S., Hrishikesh, Stephen W., Keckler, Doug, Burger, Clock Rate versus IPC: The End of the Road for Conventional Microarchitectures,weblink 27th Annual International Symposium on Computer Architecture,weblink Proceedings of the 27th Annual International Symposium on Computer Architecture, Vancouver, BC, June 10–14, 2000, 14 July 2018, which projected a maximum of 12.5% average annual CPU performance improvement between 2000 and 2014.A different concept is the processor-memory performance gap, which can be addressed by 3D integrated circuits that reduce the distance between the logic and memory aspects that are further apart in a 2D chip.BOOK, 790,weblink March 31, 2014, Nanoelectronics and Information Technology, Rainer Waser, John Wiley & Sons, 2012, no,weblink August 1, 2016, 9783527409273, Rainer Waser, Memory subsystem design requires a focus on the gap, which is widening over time.BOOK,weblink 109, March 31, 2014, Advances in Computer Systems Architecture: 11th Asia-Pacific Conference, ACSAC 2006, Shanghai, China, September 6-8, 2006, Proceedings, Chris Jesshope and Colin Egan, Springer, 2006, no,weblink August 1, 2016, 9783540400561, The main method of bridging the gap is the use of caches; small amounts of high-speed memory that houses recent operations and instructions nearby the processor, speeding up the execution of those operations or instructions in cases where they are called upon frequently. Multiple levels of caching have been developed to deal with the widening gap, and the performance of high-speed modern computers relies on evolving caching techniques.BOOK,weblink 90–91, March 31, 2014, Multiprocessor Systems-on-chips, Ahmed Amine Jerraya and Wayne Wolf, Morgan Kaufmann, 2005, no,weblink August 1, 2016, 9780123852519, These can prevent the loss of processor performance, as it takes less time to perform the computation it has been initiated to complete.BOOK,weblink 110, March 31, 2014, Impact of Advances in Computing and Communications Technologies on Chemical Science and Technology, 1999, National Academy Press, no,weblink August 1, 2016, 9780309184021, There can be up to a 53% difference between the growth in speed of processor speeds and the lagging speed of main memory access.BOOK,weblink 529, March 31, 2014, Experimental and Efficient Algorithms: Third International Workshop, WEA 2004, Angra Dos Reis, Brazil, May 25-28, 2004, Proceedings, Volume 3, Celso C. Ribeiro and Simone L. Martins, Springer, 2004, no,weblink August 1, 2016, 9783540220671, Solid-state hard drives have continued to increase in speed, from ~400 Mbit/s via SATA3 in 2012 up to ~3 GB/s via NVMe/PCIe in 2018, closing the gap between RAM and hard disk speeds, although RAM continues to be an order of magnitude faster, with single-lane DDR4 3200 capable of 25 GB/s, and modern GDDR even faster. Fast, cheap, non-volatile solid state drives have replaced some functions formerly performed by RAM, such as holding certain data for immediate availability in server farms - 1 Terabyte of SSD storage can be had for $200, while 1TB of RAM would cost thousands of dollars.WEB,weblink SSD Prices Continue to Fall, Now Upgrade Your Hard Drive!, 2018-09-03, MiniTool, en-us, 2019-03-28, WEB,weblink If you're buying or upgrading your PC, expect to pay more for RAM, Coppock, Mark, 31 January 2017,, 2019-03-28, Despite this, the speed of RAM is still a necessity for efficient computation on large, local data sets, such as analytics and machine learning, though not producing graphics for video games or VR.WEB,weblink What You Need to Know about RAM Speeds - Is Faster RAM Worth It?, 2018-10-29,, en-US, 2019-03-28,


{{See also|Flash memory#Timeline|Read-only memory#Timeline|Transistor count#Memory}}">

SRAM{| class"wikitable sortable" style"text-align:center"|+ Static random-access memory (SRAM)

! Date of introduction! Chip name! Capacity (bits)! Access time! SRAM type! Manufacturer(s)! data-sort-type="number" |Process! MOSFET! {{Abbr|Ref|Reference(s)}}|1963|{{n/a}}|1-bit|{{?}}Memory cell (computing)>CellFairchild Semiconductor>Fairchild|{{n/a}}|{{n/a}}WEBSITE=COMPUTER HISTORY MUSEUM, 19 June 2019, |1965|{{?}}|8-bit|{{?}}Bipolar junction transistor>Bipolar|IBM|{{?}}|{{n/a}}||1965|SP95|16-bit|{{?}}|Bipolar|IBM|{{?}}|{{n/a}}WEBSITE=COMPUTER HISTORY MUSEUM, 19 June 2019, |1966|TMC3162|16-bit|{{?}}Transistor–transistor logic>TTL|Transitron|{{?}}|{{n/a}}||1966|{{?}}|{{?}}|{{?}}|MOSFET|NEC|{{?}}MOSFET>MOS||1968|{{?}}|64-bit|{{?}}|MOSFET|Fairchild|{{?}}PMOS logic>PMOS||1968|{{?}}|144-bit|{{?}}|MOSFET|NEC|{{?}}NMOS logic>NMOS||1969|{{?}}|128-bit|{{?}}|Bipolar|IBM|{{?}}|{{n/a}}||1969|1101|256-bitNanosecond>ns|MOSFET|IntelNanometre>nm|PMOSWEBSITE=SEMICONDUCTOR HISTORY MUSEUM OF JAPAN TITLE=ADVANCED CMOS PROCESS TECHNOLOGY PUBLISHER=ELSEVIER PAGE=7 LAST=DATE=ARCHIVE-URL=DEAD-URL=REF=INTEL-MEMORY, |1972|2102Kibibit>kb|{{?}}|MOSFET|Intel|{{?}}|NMOS||1974|5101|1 kb|800 ns|MOSFET|Intel|{{?}}|CMOSPUBLISHER=INTEL URL=HTTP://BITSAVERS.TRAILING-EDGE.COM/COMPONENTS/INTEL/_DATABOOKS/1978_INTEL_COMPONENT_DATA_CATALOG.PDF, 27 June 2019, |1974|2102A|1 kb|350 ns|MOSFET|Intel|{{?}}Depletion-load NMOS logic>depletion)PUBLISHER=INTEL, 27 June 2019, |1975|2114|4 kb|450 ns|MOSFET|Intel|{{?}}|NMOS||1976|2115|1 kb|70 ns|MOSFET|Intel|{{?}}|NMOS (HMOS)||1976|2147|4 kb|55 ns|MOSFET|Intel|{{?}}|NMOS (HMOS)WEBSITE=SEMICONDUCTOR HISTORY MUSEUM OF JAPAN, 5 July 2019, |1977|{{?}}|4 kb|{{?}}|MOSFET|Toshiba|{{?}}|CMOS||1978|HM6147|4 kb|55 ns|MOSFET|Hitachi3 µm process>3,000 nmCMOS>twin-well)||1978|TMS4016|16 kb|{{?}}|MOSFET|Texas Instruments|{{?}}|NMOS||1980|{{?}}|16 kb|{{?}}|MOSFET|Hitachi, Toshiba|{{?}}|CMOS||1980|{{?}}|64 kb|{{?}}|MOSFETPanasonic>Matsushita|{{?}}|CMOS||1981|{{?}}|16 kb|{{?}}|MOSFET|Texas Instruments|2,500 nm|NMOS||1982|{{?}}|64 kb|{{?}}|MOSFET|Intel1.5 µm process>1,500 nm|NMOS (HMOS)||1984|{{?}}|256 kb|{{?}}|MOSFET|Toshiba|1,200 nm|CMOS||1987|{{?}}Mebibit>Mb|{{?}}|MOSFETSony, Hitachi, Mitsubishi Electric>Mitsubishi, Toshiba|{{?}}|CMOS||1990|{{?}}|4 Mb|15{{ndash}}23 ns|MOSFET|NEC, Toshiba, Hitachi, Mitsubishi|{{?}}|CMOS||1992|{{?}}|16 Mb|12{{ndash}}15 ns|MOSFET|Fujitsu, NEC|400 nm|CMOS||1995|{{?}}|4 Mb|6 nsCache (computing)>Cache (SyncBurst)|Hitachi|{{?}}|CMOS||1995|{{?}}|256 Mb|{{?}}|MOSFETSK Hynix>Hyundai|{{?}}|CMOS|">

DRAM{| class"wikitable sortable" style"text-align:center"|+ Dynamic random-access memory (DRAM)

! Date of introduction! Chip name! Capacity (bits)! DRAM type! Manufacturer(s)! data-sort-type="number" |Process!MOSFET! data-sort-type="number" | Area! {{Abbr|Ref|Reference(s)}}|1965|{{n/a}}|1-bitMemory cell (computing)>cell)|Toshiba|{{n/a}}|{{n/a}}|{{n/a}}DATE=ACCESSDATE=8 MAY 2018ARCHIVEURL=HTTPS://WEB.ARCHIVE.ORG/WEB/20170703071307/HTTP://WWW.OLDCALCULATORMUSEUM.COM/S-TOSHBC1411.HTMLDF=, Toshiba "Toscal" BC-1411 Desktop Calculator {{webarchiveweblink >date=2007-05-20 }}|1967|{{n/a}}|1-bit|DRAM (cell)|IBM|{{n/a}}MOSFET>MOS|{{n/a}}WEBSITE=SEMICONDUCTOR HISTORY MUSEUM OF JAPAN ACCESSDATE=27 JUNE 2019, |1968|{{?}}|256-bitIntegrated circuit>IC)Fairchild Semiconductor>Fairchild|{{?}}PMOS logic>PMOS|{{?}}WEBSITE=COMPUTER HISTORY MUSEUM, 19 June 2019, |1969|{{n/a}}|1-bit|DRAM (cell)|Intel|{{n/a}}|PMOS|{{n/a}}||1970Intel 1102>1102Kibibit>kb|DRAM (IC)|Intel, Honeywell|{{?}}|PMOS|{{?}}||1970Intel 1103>1103|1 kb|DRAM|IntelNanometre>nm|PMOS|10 mm²PUBLISHER=INTEL ACCESSDATE=26 JUNE 2019, The DRAM memory of Robert Dennard history-computer.comLOJEK >FIRST1=BO DATE=2007 SPRINGER SCIENCE & BUSINESS MEDIA >ISBN=9783540342588 URL=HTTPS://BOOKS.GOOGLE.COM/BOOKS?ID=2CU1OH_COV8C&PG=PA362, The i1103 was manufactured on a 6-mask silicon-gate P-MOS process with 8 μm minimum features. The resulting product had a 2,400 µm² memory cell size, a die size just under 10 mm², and sold for around $21., |1971|μPD403|1 kb|DRAM|NEC|{{?}}NMOS logic>NMOS|{{?}}WEBSITE=SEMICONDUCTOR HISTORY MUSEUM OF JAPAN, 27 June 2019, |1971|{{?}}|2 kb|DRAM|General Instrument|{{?}}|PMOS|13 mm²TITLE=IMPACT OF PROCESSING TECHNOLOGY ON DRAM SENSE AMPLIFIER DESIGN PUBLISHER=MASSACHUSETTS INSTITUTE OF TECHNOLOGY CONNECTING REPOSITORIES>CORE PAGES=149–166, 25 June 2019, |1972|2107|4 kb|DRAM|Intel|{{?}}|NMOS|{{?}}DATE=JULY 2005PUBLISHER=INTEL CORPORATIONARCHIVEDATE=AUGUST 9, 2007PUBLISHER=INTEL, 27 June 2019, |1973|{{?}}|8 kb|DRAM|IBM|{{?}}|PMOS|19 mm²||1975|2116|16 kb|DRAM|Intel|{{?}}|NMOS|{{?}}WEBSITE=NATIONAL MUSEUM OF AMERICAN HISTORY SMITHSONIAN INSTITUTION >ACCESSDATE=20 JUNE 2019, |1977|{{?}}|64 kb|DRAMNippon Telegraph and Telephone>NTT|{{?}}|NMOS|35 mm²||1979|MK4816|16 kbPseudostatic RAM>PSRAM|Mostek|{{?}}|NMOS|{{?}}PUBLISHER=MOSTEK URL=HTTP://WWW.BITSAVERS.ORG/COMPONENTS/MOSTEK/_DATABOOKS/1979_MOSTEK_MEMORY_DATA_BOOK_AND_DESIGNERS_GUIDE_MAR79.PDF, |1979|{{?}}|64 kb|DRAM|Siemens|{{?}}|VMOS|25 mm²||1980|{{?}}|256 kb|DRAM|NEC, NTT1.5 µm process>1,500 nm|NMOS|34{{ndash}}42 mm²||1981|{{?}}|288 kb|DRAM|IBM|{{?}}|MOS|25 mm²WEBSITE=NATIONAL MUSEUM OF AMERICAN HISTORY SMITHSONIAN INSTITUTION >ACCESSDATE=20 JUNE 2019, |1983|{{?}}|64 kb|DRAM|Intel1.5 µm process>1,500 nm|CMOS|20 mm²||1983|{{?}}|256 kb|DRAM|NTT|{{?}}|CMOS|31 mm²|Mebibit>Mb|DRAM|Hitachi|{{?}}|MOS|{{?}}WEBSITE=COMPUTER HOPE DATE=1987 ISSUE=3–4 URL=HTTPS://BOOKS.GOOGLE.COM/BOOKS?ID=FA0KAQAAIAAJ QUOTE=THE ANNOUNCEMENT OF 1M DRAM IN 1984 BEGAN THE ERA OF MEGABYTES., 1 µm process>1,000 nm|NMOS|74{{ndash}}76 mm²TITLE=EXPERIMENTAL MEMORY CHIPS REACH 1 MEGABIT: AS THEY BECOME LARGER, MEMORIES BECOME AN INCREASINGLY IMPORTANT PART OF THE INTEGRATED CIRCUIT BUSINESS, TECHNOLOGICALLY AND ECONOMICALLY SCIENCE (JOURNAL)>SCIENCE VOLUME=224 PAGES=590–592 PMID=17838349, 0036-8075, 800 nanometer>800 nm|CMOS|53 mm²||1984|TMS4161|64 kbDual-ported RAM>DPRAM (VRAM)|Texas Instruments|{{?}}|NMOS|{{?}}PUBLISHER=TEXAS INSTRUMENTS PAGES=4–15 WEBSITE=IEEE COMPUTER SOCIETY, 29 June 2019, PUBLISHER=NEC ELECTRONICS WEBSITE=GOOGLE PATENTS, 21 June 2019, DATE=1987 ISSUE=3–4 URL=HTTPS://BOOKS.GOOGLE.COM/BOOKS?ID=FA0KAQAAIAAJ, University Microfilms, |1986|{{?}}|4 Mb|DRAM|NEC|800 nm|NMOS|99 mm²||1986|{{?}}|4 Mb|DRAM|Texas Instruments, Toshiba|1,000 nm|CMOS|100{{ndash}}137 mm²||1987|{{?}}|16 Mb|DRAM|NTT|700 nm|CMOS|148 mm²||1991|{{?}}|64 Mb|DRAMPanasonic>Matsushita, Mitsubishi, Fujitsu, Toshiba|400 nm|CMOS|{{?}}WEBSITE=STOL (SEMICONDUCTOR TECHNOLOGY ONLINE), 25 June 2019, |1993|{{?}}|256 Mb|DRAM|Hitachi, NEC250 nanometer>250 nm|CMOS|{{?}}||1995|{{?}}|4 Mb|DPRAM (VRAM)|Hitachi|{{?}}|CMOS|{{?}}PUBLISHER=SMITHSONIAN INSTITUTION ACCESSDATE=27 JUNE 2019, Gibibit>Gb|DRAM|NEC|250 nm|CMOS|{{?}}|weblink" title="">Breaking the gigabit barrier, DRAMs at ISSCC portend major system-design impact. (dynamic random access memory; International Solid-State Circuits Conference; Hitachi Ltd. and NEC Corp. research and development) Highbeam Business, January 9, 1995|1997|{{?}}|4 GbQuad-level cell>QLC|NEC|150 nm|CMOS|{{?}}||1998|{{?}}|4 Gb|DRAM|Hyundai|{{?}}|CMOS|{{?}}|Toshiba|{{?}}|CMOS|{{?}}ACCESSDATE=29 JUNE 2019 DATE=24 JUNE 2001, en-UK, 100 nm|CMOS|{{?}}PUBLISHER=MIT ACCESSDATE=29 JUNE 2019,


{{Transcluded section|Synchronous dynamic random-access memory|part=yes}}{{trim|{{#section::Synchronous dynamic random-access memory|SDRAM timeline}} }}

See also

{{Columns-list|colwidth=30em| }}



External links

  • {{Commons-inline|RAM}}
{{Basic computer components}}{{Authority control}}

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