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Processor register
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{{Multiple issues|{{more citations needed|date=March 2008}}{{cleanup|date=January 2012}}{{Update|date=March 2017}}}}In computer architecture, a processor register is a quickly accessible location available to a computer's central processing unit (CPU). Registers usually consist of a small amount of fast storage, although some registers have specific hardware functions, and may be read-only or write-only. Registers are typically addressed by mechanisms other than main memory, but may in some cases be assigned a memory address e.g. DEC PDP-10, ICT 1900.Almost all computers, whether load/store architecture or not, load data from a larger memory into registers where it is used for arithmetic operations and is manipulated or tested by machine instructions. Manipulated data is then often stored back to main memory, either by the same instruction or by a subsequent one. Modern processors use either static or dynamic RAM as main memory, with the latter usually accessed via one or more cache levels.Processor registers are normally at the top of the memory hierarchy, and provide the fastest way to access data. The term normally refers only to the group of registers that are directly encoded as part of an instruction, as defined by the instruction set. However, modern high-performance CPUs often have duplicates of these "architectural registers" in order to improve performance via register renaming, allowing parallel and speculative execution. Modern x86 design acquired these techniques around 1995 with the releases of Pentium Pro, Cyrix 6x86, Nx586, and AMD K5.A common property of computer programs is locality of reference, which refers to accessing the same values repeatedly and holding frequently used values in registers to improve performance; this makes fast registers and caches meaningful.JOURNAL, A Survey of Techniques for Designing and Managing CPU Register File, Concurrency and Computation, 29, 4, e3906, 10.1002/cpe.3906, Wiley, 2016, en, Mittal, Sparsh,weblink Allocating frequently used variables to registers can be critical to a program's performance; this register allocation is performed either by a compiler in the code generation phase, or manually by an assembly language programmer.

{{Anchor|RS}}Register size

Registers are normally measured by the number of bits they can hold, for example, an "8-bit register", "32-bit register" or a "64-bit register" or even more. In some instruction sets, the registers can operate in various modes breaking down its storage memory into smaller ones (32-bit into four 8-bit one for instance) to which multiple data (vector, or one dimensional array of data) can be loaded and operated upon at the same time. Typically it is implemented by adding extra registers that map their memory into bigger one. Processors that have the ability to execute single instruction on multiple data are called vector processors.

{{Anchor|GPR}}Types of registers

A processor often contains several kinds of registers, which can be classified according to their content or instructions that operate on them:
  • User-accessible registers can be read or written by machine instructions. The most common division of user-accessible registers is into data registers and address registers.
    • {{vanchor|Data register}}s can hold numeric data values such as integer and, in some architectures, floating-point values, as well as characters, small bit arrays and other data. In some older and low end CPUs, a special data register, known as the accumulator, is used implicitly for many operations.
    • {{vanchor|Address register}}s hold addresses and are used by instructions that indirectly access primary memory.
      • Some processors contain registers that may only be used to hold an address or only to hold numeric values (in some cases used as an index register whose value is added as an offset from some address); others allow registers to hold either kind of quantity. A wide variety of possible addressing modes, used to specify the effective address of an operand, exist.
      • The stack pointer is used to manage the run-time stack. Rarely, other data stacks are addressed by dedicated address registers, see stack machine.
    • General-purpose registers (GPRs) can store both data and addresses, i.e., they are combined data/address registers and rarely the register file is unified to include floating point as well.
    • Status registers hold truth values often used to determine whether some instruction should or should not be executed.
    • {{vanchor|Floating-point register|FLOATING_POINT_REGISTER|floating point register}}s (FPRs) store floating point numbers in many architectures.
    • Constant registers hold read-only values such as zero, one, or pi.
    • {{visible anchor|Vector registers}} hold data for vector processing done by SIMD instructions (Single Instruction, Multiple Data).
    • Special-purpose registers (SPRs) hold program state; they usually include the program counter, also called the instruction pointer, and the status register; the program counter and status register might be combined in a program status word (PSW) register. The aforementioned stack pointer is sometimes also included in this group. Embedded microprocessors can also have registers corresponding to specialized hardware elements.
    • In some architectures, model-specific registers (also called machine-specific registers) store data and settings related to the processor itself. Because their meanings are attached to the design of a specific processor, they cannot be expected to remain standard between processor generations.
    • Memory Type Range Registers (MTRRs)
  • Internal registers – registers not accessible by instructions, used internally for processor operations.
  • Architectural register{{anchor|ARCHITECTURAL}} - The registers visible to software defined by an architecture may not correspond to the physical hardware, if there is register renaming being performed by underlying hardware.
Hardware registers are similar, but occur outside CPUs.In some architectures (such as SPARC and MIPS), the first or last register in the integer register file is a pseudo-register in a way that it is hardwired to always return zero when read (mostly to simplify indexing modes), and it cannot be overwritten. In Alpha this is also done for the floating-point register file. As a result of this, register files are commonly quoted as having one register more than how many of them are actually usable; for example, 32 registers are quoted when only 31 of them fit within the above definition of a register.

Examples

The following table shows the number of registers in several mainstream CPU architectures. Note that in x86-compatible processors the stack pointer (ESP) is counted as an integer register, even though there are a limited number of instructions that may be used to operate on its contents. Similar caveats apply to most architectures.Although all of the above listed architectures are different, almost all are a basic arrangement known as the Von Neumann architecture, first proposed by the Hungarian-American mathematician John von Neumann. It is also noteworthy that the number of registers on GPUs is much higher than that on CPUs."A Survey of Techniques for Architecting and Managing GPU Register File", IEEE TPDS, 2016{| class="wikitable sortable" align="left"! Architecture ! GPRs/data+address registers! FP registers! Notes
AT&T Hobbit >| Stack machine
Cray-1HTTP://WWW.BITSAVERS.ORG/PDF/CRAY/CRAY-1/2240004C_CRAY-1_HARDWARE_REFERENCE_NOV77.PDFPUBLISHER=CRAY RESEARCH| Scalar data registers can be integer or floating-point; also 64 scalar scratch-pad T registers and 64 address scratch-pad B registers
4004HTTP://BITSAVERS.ORG/PDF/INTEL/MCS4/MCS-4_USERSMANUAL_FEB73.PDFPUBLISHER=INTEL| Register A is for general purpose, while r0–r15 registers are for the address and segment.
8008HTTP://BITSAVERS.ORG/PDF/INTEL/MCS8/8008USERSMANUALREV4_NOV73.PDFPUBLISHER=INTELACCESSDATE=JANUARY 23, 2014, 1 accumulator, 6 others 0 The A register is an accumulator to which all arithmetic is done; the H and L registers can be used in combination as an address register; all registers can be used as operands in load/store/move/increment/decrement instructions and as the other operand in arithmetic instructions. There is no FP unit available.
8080HTTP://BITSAVERS.ORG/PDF/INTEL/MCS80/98-153B_INTEL_8080_MICROCOMPUTER_SYSTEMS_USERS_MANUAL_197509.PDFPUBLISHER=INTELACCESSDATE=JANUARY 23, 2014, 1 accumulator, 6 others 0 Plus a stack pointer. The A register is an accumulator to which all arithmetic is done; the register pairs B+C, D+E, and H+L, can be used as address registers in some instructions; all registers can be used as operands in load/store/move/increment/decrement instructions and as the other operand in arithmetic instructions. Some instructions only use H+L; another instruction swaps H+L and D+E. Floating point processors intended for the 8080 were Intel 8231, AMD Am9511 and Intel 8232. They were also readily usable with the Z80 and similar processors.
iAPX432 >| Stack machine
X86#16-bit>16-bit x86HTTP://WWW.BITSAVERS.ORG/PDF/INTEL/80286/210498-005_80286_AND_80287_PROGRAMMERS_REFERENCE_MANUAL_1987.PDF>TITLE=80286 AND 80287 PROGRAMMER'S REFERENCE MANUALYEAR=1987, 8 stack of 8 (if FP present) Intel 8086/Intel 8088>8088, Intel 80186/Intel 80188>80188, Intel 80286, with Intel 8087>8087, Intel 80187 or Intel 80287>80287 for floating-point, with an 80-bit wide, 8 deep register stack with some instructions able to use registers relative to the top of the stack as operands; without 8087/80187/80287, no floating-point registers
IA-32HTTP://WWW.INTEL.COM/CONTENT/WWW/US/EN/PROCESSORS/ARCHITECTURES-SOFTWARE-DEVELOPER-MANUALS.HTMLPUBLISHER=INTEL, 8 stack of 8 (if FP present), 8 (if SSE/MMX present) Intel 80386 required Intel 80387>80387 for floating-point, later processors had built-in floating point, with both having an 80-bit wide, 8 deep register stack with some instructions able to use registers relative to the top of the stack as operands. The Pentium III and later had the SSE with additional 128-bit XMM registers.
x86-64HTTP://SUPPORT.AMD.COM/TECHDOCS/24592.PDFPUBLISHER=AMDAdvanced Vector Extensions>AVX/AVX2 and 512-bit ZMM0-ZMM31 registers with Advanced Vector Extensions#Advanced Vector Extensions 512.HTTPS://SOFTWARE.INTEL.COM/SITES/DEFAULT/FILES/MANAGED/C5/15/ARCHITECTURE-INSTRUCTION-SET-EXTENSIONS-PROGRAMMING-REFERENCE.PDFPUBLISHER=INTEL, January 2018,
Xeon PhiHTTP://SOFTWARE.INTEL.COM/SITES/DEFAULT/FILES/FORUM/278102/327364001EN.PDFPUBLISHER=INTEL| Including 32 256/512-bit ZMM registers with AVX-512.
Fairchild F8 >PUBLISHER=FAIRCHILD MOS MICROCOMPUTER DIVISION, 1977,
Geode GX >Media GX/4x86/cx5x86>5x86 is the emulation of 486/Pentium compatible processor made by Cyrix/National Semiconductor. Like Transmeta, the processor had a translation layer that translated x86 code to native code and executed it.{{citation needed3DNow! from AMD. The native processor only contains 1 data and 1 address register for all purpose and translated into 4 paths of 32-bit naming register r1 (base), r2 (data), r3 (back pointer), and r4 (stack pointer) within scratchpad sram for integer operation and uses the L1 cache for x86 code emulation(note that it's not compatible with some 286/386/486 instructions in real mode).{{citation needed>date=February 2016}} Later the design was abandoned after AMD acquired the IP from National Semiconductor and branded it with Athlon core in embedded market.
V.Smile>SunPlus SPG 0 6 stack + 4 SIMD A 16-bit wide, 32-bit address space stack machine processor from the Taiwanese company Sunplus Technology, it can be found on Vtech's V.Smile line for educational purpose and the video game console Mattel HyperScan, and XaviXPORT. it does lack any general purpose register or internal register for naming/renaming but its Floating Point Unit has 80-bit 6 stage stack and four 128-bit VLIW SIMD register on a vertex shader co-processor.
Nuon (DVD technology)>VM Labs Nuon 0 1 a 32-bit stack machine processor that developed by VM labs for specialized on multimedia purpose. It can be found on the company's own Nuon DVD player console line and Game Wave Family Entertainment System from ZaPit games. The design was heavy influence by Intel's MMX technology, it contained a 128 bytes unified stack cache for both vector and scalar instructions. the unified cache can be divided as 8 128-bit vector register or 32 32bit SIMD scalar register through bank renaming, no integer register found in this architecture.
Nios IIHTTPS://WWW.ALTERA.COM/EN_US/PDFS/LITERATURE/HB/NIOS2/N2CPU_NII5V1.PDFPUBLISHER=ALTERAPUBLISHER=ALTERAdate=February 2016}} and has 31 32-bit GPRs, with register 0 being hardwired to zero and 8 64-bit floating point registers{{citation needed|date=February 2016}}
Motorola 6800HTTP://BITSAVERS.ORG/PDF/MOTOROLA/6800/MOTOROLA_M6800_PROGRAMMING_REFERENCE_MANUAL_M68PRM(D)_NOV76.PDF PUBLISHER=MOTOROLA ACCESSDATE=MAY 18, 2015, 2 data, 1 index 0 Plus a stack pointer
Motorola 68kHTTP://WWW.FREESCALE.COM/FILES/ARCHIVES/DOC/REF_MANUAL/M68000PRM.PDFPUBLISHER=MOTOROLAACCESSDATE=JUNE 13, 2015, 8 data (d0-d7), 8 address (a0-a7) 8 (if FP present) Address register 8 (a7) is the stack pointer. 68000, 68010, 68012, 68020, and 68030 require an FPU for floating point; 68040 had FPU built in. FP registers are 80-bit.
SuperH>SH 16-bit 1 6
Emotion Engine >| The Emotion Engine's main core (VU0) is a heavily modified DSP general core that's for general background task and it contains one 64 bit accumulator, two general data registers and one 32 bit program counter. A modified MIPS III executable core(VU1) is for game data and protocol control and it contains 32 entries 32-bit general-purpose registers for integer computation and 32 entries 128-bit SIMD registers for storing SIMD instruction, streaming data value and some integer calculation value. one accumulator register for connecting general floating-point computation to vector register file on co-processor. The coprocessor is built via 32 entries 128-bit vector register file(can only store vector value that pass from accumulator in cpu. ) and no integer register is built in. Both vector co-processor(VPU 0/1) and emotion engine's entire main processor module(VU0 + VU1 + VPU0 + VPU1) are built based on modified MIPS instructions set and accumulator in this case is not general purpose but control status.
CUDA}}CUDA 1 8/16/32/64/128 Each CUDA core contains a single 32/64-bit integer data register while the floating point unit contains a much larger number of registers:
  • the Tesla 1.0-based G8x contains 8×128-bit HDR vector registers,
  • the Tesla 2.0-based GT200 increased the count to 16×128-bit
  • Fermi extended the register width to 256 bits and increased the register count to 32, (32×256-bit)
  • Kepler increased it to 64. (64×256-bit)
  • Maxwell contains a massive amount of 128 512-bit vector registers. (128×512-bit)
  • Pascal: ?
  • Volta: ?{{citation needed|date=November 2016}}
IBM/360 >System/370 through System/390; FP was optional in System/360, and always present in S/370 and later. In processors with the Vector Facility, there are 16 vector registers containing a machine-dependent number of 32-bit elements.HTTP://BITSAVERS.TRAILING-EDGE.COM/PDF/IBM/370/SA22-7125-3_VECTOR_OPERATIONS_AUG88.PDFPUBLISHER=IBM, January 5, 2014,
z/Architecture >| 64-bit version of S/360 and successors; it increased the number of floating-point registers to 16.
MMIXHTTP://MMIX.CS.HM.EDU| An instruction set designed by Donald Knuth in the late 1990s for pedagogical purposes.
NS320xxHTTP://BITSAVERS.ORG/COMPONENTS/NATIONAL/_DATABOOKS/1986_NATIONAL_NS32000_DATABOOK.PDFPUBLISHER=NATIONAL SEMICONDUCTOR, 8 8 (if FP present)
Xelerated X10 >date=March 2019}}
Parallax Propeller >| An eight core 8/16 bit sliced stack machine controller with simple logic circus inside, have eight cog counter(core) and each contain three 8/16 bit special control registers with 32 bit x 512 stack ram however it does not carrying any general register for integer purpose. unlike most of shadow register file in modern processor and multi core system, all these stack ram in cog can be accessed in instruction level which all these cog can act as one big single general purpose core if necessary. Floating point unit is external and it contain two 80 bit vector register.
Itanium >| And 64 1-bit predicate registers and 8 branch registers. The FP registers are 82-bit.
SPARC >| Global register 0 is hardwired to 0. Uses register windows.
IBM POWER Instruction Set Architecture>IBM POWER 32 32 And 1 link and 1 count register.
Power ISA >AltiVec>Vector facility also have 32 128-bit vector registers,
Blackfin >| containing two external uncore 40 bit accumulator, but non are general purpose. Support 64 bit RISC architecture ISA, vector register are 256 bit.
IBM Cell SPE >128}} 128 GPRs, which can hold integer, address, or floating-point valuesHTTPS://WWW-01.IBM.COM/CHIPS/TECHLIB/TECHLIB.NSF/TECHDOCS/76CA6C7304210F3987257060006F2C44/$FILE/SPU_ISA_V1.2_27JAN2007_PUB.PDF>TITLE=SYNERGISTIC PROCESSOR UNIT INSTRUCTION SET ARCHITECTURE VERSION 1.2DATE=JANUARY 27, 2007,
DEC PDP-10>PDP-10 16 0 All may be used generally (integer, float, stack pointer, jump, indexing, etc.). Every 36-bit memory (or register) word can also be manipulated as a half-word, which can be considered an (18-bit) address. Other word interpretations are used by certain instructions. In the original PDP-10 processors, these 16 GPRs also corresponded to main (i.e. Magnetic-core memory) memory locations 0-15; a hardware option called "fast memory" implemented the registers as separate ICs, and references to memory locations 0-15 referred to the IC registers. Later models implemented the registers as "fast memory" and continued to make memory locations 0-15 refer to them. Movement instructions take (register, memory) operands: {{code>MOVE 1,2}} is register-register, and {{code|MOVE 1,1000}} is memory-to-register.
DEC PDP-11>PDP-11 8 0 R7 is actually the Program Counter. Any register can be a stack pointer but R6 is used for hardware interrupts and traps.
DEC VAX>VAX 16 0 Three of the registers have special uses: R12 (Argument Pointer), R13 (Frame Pointer), and R14 (Stack Pointer), while R15 refers to the Program Counter.
DEC Alpha>Alpha 31 31 Registers R31 (integer) and F31 (floating-point) are hardwired to zero.
MOS Technology 6502>6502 1 data, 2 index 0 6502's content A (Accumulator) register for main purpose data store and memory address (8-bit data/16-bit address), X,Y are indirect and direct index registers (respectively) and SP register are specific index only.
65C816>W65C816S 1 0 65C816 is the 16-bit successor of the 6502. X,Y, D (Direct Page register) are condition register and SP register are specific index only. main accumulator extended to 16-bit (B) while keep 8-bit (A) for compatibility and main register can now address up to 24-bit (16-bit wide data instruction/24-bit memory address).
65k >| Direct successor of 6502, 65002 only content A (Accumulator) register for main purpose data store and extend data wide to 32-bit and 64-bit instruction wide, support 48-bit virtual address in software mode, X,Y are still condition register and remain 8-bit and SP register are specific index but increase to 16-bit wide.
Media-embedded processor>MeP 4 8 Media-embedded processor was a 32 bit processor developed by toshiba, a modded 8080 instruction set with only A, B, C, D register available through all mode(8/16/32 bit) and incompatible with x86, however it contain 80 bit floating point unit that is x87 compatible.
PIC microcontroller >|
Atmel AVR>AVR microcontroller 32 0
ARM architecture>ARM 32-bit (ARM/A32, Thumb/T32) 14 Varies (up to 32) r15 is the program counter, and not usable as a GPR; r13 is the stack pointer; r8-r13 can be switched out for others (banked) on a processor mode switch. Older versions had 26-bit addressing,HTTP://INFOCENTER.ARM.COM/HELP/TOPIC/COM.ARM.DOC.IHI0042D/IHI0042D_AAPCS.PDF>TITLE=PROCEDURE CALL STANDARD FOR THE ARM ARCHITECTUREARM HOLDINGS>DATE=30 NOVEMBER 2013, 27 May 2013, and used upper bits of the program counter (r15) for status flags, making that register 32-bit.
ARM architecture>ARM 64-bit (A64)HTTP://INFOCENTER.ARM.COM/HELP/TOPIC/COM.ARM.DOC.IHI0055A/IHI0055A_AAPCS64.PDF>TITLE=PROCEDURE CALL STANDARD FOR THE ARM 64-BIT ARCHITECTUREDATE=22 MAY 2013| Register r31 is the stack pointer or hardwired to 0, depending on the context.
MIPS architecture>MIPS 31 32 Register 0 is hardwired to 0.
Adapteva>Epiphany colspan="2" {{dunno| Each instruction controls whether registers are interpreted as integers or single precision floating point. Architecture is scalable to 4096 cores with 16 and 64 core implementations currently available.
{{Clear}}

Register usage

The number of registers available on a processor and the operations that can be performed using those registers has a significant impact on the efficiency of code generated by optimizing compilers. The Strahler number of an expression tree gives the minimum number of registers required to evaluate that expression tree.

See also

References

{{Reflist|30em}}{{CPU technologies}}{{X86 assembly topics}}{{Authority control}}

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